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([171.76.93.102]) by smtp.gmail.com with ESMTPSA id o186-20020a62cdc3000000b0050dc7628171sm10374129pfg.75.2022.07.18.22.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 22:48:24 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-always-on Date: Tue, 19 Jul 2022 11:17:28 +0530 Message-Id: <20220719054729.2224766-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220719054729.2224766-1-apatel@ventanamicro.com> References: <20220719054729.2224766-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220718_224828_449727_810E1BF3 X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We add an optional DT property riscv,timer-always-on which if present in CPU DT node then CPU timer is always powered-on and never loses context. Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..33832b8dfaab 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,12 @@ properties: - rv64imac - rv64imafdc + riscv,timer-always-on: + type: boolean + description: + If present, the timer is powered through an always-on power + domain, therefore it never loses context. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C4A3C43334 for ; Tue, 19 Jul 2022 05:48:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236733AbiGSFs1 (ORCPT ); Tue, 19 Jul 2022 01:48:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236713AbiGSFs0 (ORCPT ); Tue, 19 Jul 2022 01:48:26 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 037FF25589 for ; Mon, 18 Jul 2022 22:48:26 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id e16so12564940pfm.11 for ; Mon, 18 Jul 2022 22:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Zv1KPN9JiNDXsrpx/KpRv4jlVQ/XgtQ+la2iBvvbEo=; b=aPmyhgHbEj3yjha+RdH7+WmsgzNU6UK2PdYcjlAmGBwYMtEf1UUTaGFvA/5q3/uqf2 TSB6Pb0KkVqQxl+mHM+p05+aB2P5iNDR4JPwth096jqb6fK+ei29DWXX6/m5v9EsqHiI 4EJ/DM1d9n7Rq270JbzZLvMOQyJDkGEGWn0b9gPk0e8WV0U9tV5+yXOwjV8pN4Ua2ZPA ZX5FKnH5IeeNqaVG+9NH1B6+Sz/m4+M852tl3ArR+1lescplIrffsGg4Y9JW/C4xwctn gGtD4KLl+OQq9rj6VoPFcNUtmF+IrtEbwKLvDpQcEIUsvhbJOXyJwOzd5tEghk+vQCC2 gGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Zv1KPN9JiNDXsrpx/KpRv4jlVQ/XgtQ+la2iBvvbEo=; b=j7WYN0lWOgu1lFKYF8HU2TIhcMw+yNhYfOGf5k9XZahnc1OqXMcI6r0xGXd1bKwfuw wrL48BXw7RvOFMA4BKCnVsYv6x/d939WbotzlMH1fhlFvIBeiUxle9zIDbatPjKBFnPG dJNU9pB+rikJy+FuC986OBJc80fgY6MGFwyBBgC9eK3FQwsrYF81C9febrodylbgjFha /gtc9+9ZRBAQtAsBu2xY32Ox6bOVhury3untp1luL5UxbWjfZH7X6IkfIbG9wu6IZXJU O4DifaIsmeO8MhF3eV9szEKahdqzwqh0gGk55NB1QlR30P6ds1zs8xWpEhxrKNWndigh X2Og== X-Gm-Message-State: AJIora8aqY9wGUlxiTn3rbjgNeWLJh0VROfGYPjCEFInDjMCJ5a6mguU Xi9n6nGVu69FUYSasaMmJTXj/g== X-Google-Smtp-Source: AGRyM1swatdkW28ipNZyiwyjPCdj/wjSf0JTm3UtSlnt0QiJb65SJO6lfU4nMttdr1PWPl6x72yPxg== X-Received: by 2002:aa7:8887:0:b0:52b:17e8:fc7 with SMTP id z7-20020aa78887000000b0052b17e80fc7mr28107122pfe.35.1658209705381; Mon, 18 Jul 2022 22:48:25 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.93.102]) by smtp.gmail.com with ESMTPSA id o186-20020a62cdc3000000b0050dc7628171sm10374129pfg.75.2022.07.18.22.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 22:48:24 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-always-on Date: Tue, 19 Jul 2022 11:17:28 +0530 Message-Id: <20220719054729.2224766-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220719054729.2224766-1-apatel@ventanamicro.com> References: <20220719054729.2224766-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add an optional DT property riscv,timer-always-on which if present in CPU DT node then CPU timer is always powered-on and never loses context. Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..33832b8dfaab 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,12 @@ properties: - rv64imac - rv64imafdc + riscv,timer-always-on: + type: boolean + description: + If present, the timer is powered through an always-on power + domain, therefore it never loses context. + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.34.1