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From: Jakub Kicinski <kuba@kernel.org>
To: <richardcochran@gmail.com>
Cc: Naveen Mamindlapalli <naveenm@marvell.com>, <davem@davemloft.net>,
	<edumazet@google.com>, <pabeni@redhat.com>,
	<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<sgoutham@marvell.com>
Subject: Re: [net-next PATCH v2 0/4] Add PTP support for CN10K silicon
Date: Tue, 2 Aug 2022 21:44:20 -0700	[thread overview]
Message-ID: <20220802214420.10e3750f@kernel.org> (raw)
In-Reply-To: <20220802121439.4d784f47@kernel.org>

On Tue, 2 Aug 2022 12:14:39 -0700 Jakub Kicinski wrote:
> On Sat, 30 Jul 2022 17:27:54 +0530 Naveen Mamindlapalli wrote:
> > This patchset adds PTP support for CN10K silicon, specifically
> > to workaround few hardware issues and to add 1-step mode.  
> 
> Hi Richard, any thoughts on this one? We have to make a go/no-go
> decision on it for 6.0.

Oh, well. These will have to wait until after the merge window then :(

  reply	other threads:[~2022-08-03  4:44 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-30 11:57 [net-next PATCH v2 0/4] Add PTP support for CN10K silicon Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 1/4] octeontx2-af: return correct ptp timestamp " Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 2/4] octeontx2-pf: Add support for ptp 1-step mode on " Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 3/4] octeontx2-af: Add PTP PPS Errata workaround " Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 4/4] octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly Naveen Mamindlapalli
2022-08-02 19:14 ` [net-next PATCH v2 0/4] Add PTP support for CN10K silicon Jakub Kicinski
2022-08-03  4:44   ` Jakub Kicinski [this message]
2022-08-04  3:08     ` Richard Cochran
2022-08-04 16:06       ` Jakub Kicinski

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