From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB770C19F2A for ; Thu, 4 Aug 2022 14:29:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E684A8485F; Thu, 4 Aug 2022 16:28:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="xI1kOs2R"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2718084863; Thu, 4 Aug 2022 16:28:47 +0200 (CEST) Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5CF808485A for ; Thu, 4 Aug 2022 16:28:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102c.google.com with SMTP id q7-20020a17090a7a8700b001f300db8677so5803781pjf.5 for ; Thu, 04 Aug 2022 07:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+C0wegH9ETELdYcO2y+fqOabPqVe8TOMLFQoRXRh8+A=; b=xI1kOs2RFCnGIOWPXA8yPo0PgV7rq6XJPP4kajjYUwoIn8KkKL71fOHVkTEmQg7ZHP XUQZAEwcGBn9+w0YicrOz21XGXhiIhEUSCnSyuXDYephh+2iPRVrfDIH4uX0/79wGkpM NqNmboPhrzzXmYN7mVK+7Kz95YU+8li37XSK0MOy0zermLw90I1+k8H3selXHju+ofrQ kyiEHgVfIaxpfpDhlHyX+irmjehlZSAyFggHHDRCvxOipkeT/b+unjjQYfZQihBKy4G6 9Tl07NJzyDkQ+5YiOucf+Oue8CXtR16IFBMOfiebch5f9bwvQ/XxHZjo5Ltsf1Mu1yLZ rF4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+C0wegH9ETELdYcO2y+fqOabPqVe8TOMLFQoRXRh8+A=; b=CwA/k4HzD/F9s4orOvFK+Mw4NsT66j0FQ3qV+KYvUrOf0UP3x8Efh478Xwi/DBn/9E OUO/J7F47cXOsstFK7czc+xaplP8n5ybCaNHbxnKb7fhH1B40IKum80jWqSI4ky1Strq O53cU5/ktCcws6ujDt158VgnKm2YblCpfufdE74RcEvaSsKrckDfmdwcg9IauxJGn/Ta gY489ES++B3DysTpDU3ubYj2HruvgA8QdQ1UUjOqdY1SNIksrIytCZgH1b6tV/WMbkYV P+DiA7FfiNaCIYQCYz+jHwq/utdcjl70tR3jljzmA+o4AwZfmWHTZfx0IsvpEcYywAkg qxvw== X-Gm-Message-State: ACgBeo3SAXVQKhM9bunAJKKCEHPjJYVLGedDeXr+QZAFEN0h2Fa/i8Ai rjUsv1wZhUoKluqM5dCAUlEjYUONY7Op5A== X-Google-Smtp-Source: AA6agR5r+9g5Gnmkku7ma/1c7UZu36HrzI3ACFMc/kKzUIDkCJAOODHaCoPpV//lZIePXizCsAf7ew== X-Received: by 2002:a17:902:bf0b:b0:16e:f089:87f2 with SMTP id bi11-20020a170902bf0b00b0016ef08987f2mr2156279plb.87.1659623323681; Thu, 04 Aug 2022 07:28:43 -0700 (PDT) Received: from localhost.localdomain ([122.162.196.218]) by smtp.gmail.com with ESMTPSA id h185-20020a6253c2000000b0052cdb06c125sm1013549pfb.159.2022.08.04.07.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Aug 2022 07:28:43 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, jorge.ramirez.ortiz@gmail.com, sjg@chromium.org, trini@konsulko.com, stephan@gerhold.net, mario.six@gdsys.cc, dsankouski@gmail.com, robert.marko@sartura.hr, luka.kovacic@sartura.hr, luka.perkov@sartura.hr, jh80.chung@samsung.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, mworsfold@impinj.com, lgillham@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH 08/13] dts: qcs404-evb: Add USB controller and PHY nodes Date: Thu, 4 Aug 2022 19:57:16 +0530 Message-Id: <20220804142721.536556-9-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220804142721.536556-1-sumit.garg@linaro.org> References: <20220804142721.536556-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean QCS404 SoC provides support for two USB controllers: one USB3 and the other one being USB2. The USB3 controller supports further 2 PHY: one high speed PHY and the other super speed PHY. The USB2 controller supports a single high speed PHY. So add corresponding DT nodes. Signed-off-by: Sumit Garg --- arch/arm/dts/qcs404-evb.dts | 87 +++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 1b280efff6..2e3a0c6958 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -52,6 +52,7 @@ reg = <0x1800000 0x80000>; #address-cells = <0x1>; #size-cells = <0x0>; + #clock-cells = <1>; }; reset: gcc-reset@1800000 { @@ -81,6 +82,92 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; }; + + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + #phy-cells = <0>; + reg = <0x78000 0x400>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ahb", "pipe"; + resets = <&reset GCC_USB3_PHY_BCR>, + <&reset GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7a000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&reset GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7c000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_QUSB2_PHY_BCR>, + <&reset GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + }; + + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x7678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x7580000 0xcd00>; + phys = <&usb2_phy_prim>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x79b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x78c0000 0xcc00>; + phys = <&usb2_phy_sec>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + }; + }; }; }; -- 2.25.1