From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D6BEC19F2A for ; Sun, 7 Aug 2022 14:44:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 35FA484085; Sun, 7 Aug 2022 16:44:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=suse.de header.i=@suse.de header.b="GaC47eXn"; dkim=permerror (0-bit key) header.d=suse.de header.i=@suse.de header.b="s6jX+2gN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 476BA841A4; Sun, 7 Aug 2022 16:44:08 +0200 (CEST) Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 141E383965 for ; Sun, 7 Aug 2022 16:44:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=msuchanek@suse.de Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id C555833E4F; Sun, 7 Aug 2022 14:44:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1659883445; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type; bh=N7iQvytwqglBw2kh8N4LmMzA1BYGLnvcZUdx8Bwj0Pg=; b=GaC47eXnMxTZCKE1iOBVyGkqbxJgNJ5eruN3VRBqSbv0czDLG0TWTUQPDj4JmfaQl/Code 3Tyww5O49DARP1lIHqWnKm2l/bLZCetuZz0vkWRBF+tDxRy/QLi7PbSJ4sXwpqJn8ZP7XD gfpOfUfovbJczH+PihO+Afu1RDylvrU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1659883445; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type; bh=N7iQvytwqglBw2kh8N4LmMzA1BYGLnvcZUdx8Bwj0Pg=; b=s6jX+2gNVZPmhwdrBCXQrKGEGpar0cxlw7xpatfpQ6iPOzGMifTJ2HwEiP1qdG+xm+rq1p zUlAdW5cDNj092Ag== Received: from kitsune.suse.cz (kitsune.suse.cz [10.100.12.127]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 802702C141; Sun, 7 Aug 2022 14:44:05 +0000 (UTC) Date: Sun, 7 Aug 2022 16:44:04 +0200 From: Michal =?iso-8859-1?Q?Such=E1nek?= To: u-boot@lists.denx.de Cc: Kever Yang Subject: rk3399 TPL memory setup code triggers clock frequency limit assertion Message-ID: <20220807144404.GJ17705@kitsune.suse.cz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hello, when compiled with clock debug rk3399 cannot be booted because memory setup code triggers clock assertion: U-Boot TPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17) TPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz TPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz TPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz TPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz TPL PLL at ff760040: fbdiv=12, refdiv=1, postdiv1=3, postdiv2=2, vco=288000 khz, output=48000 khz drivers/clk/rockchip/clk_rk3399.c:347: rkclk_set_pll: Assertion `vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX' failed.Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride TPL PLL at ff760040: fbdiv=50, refdiv=1, postdiv1=3, postdiv2=1, vco=1200000 khz, output=400000 khz lpddr4_set_rate: change freq to 400000000 mhz 0, 1 TPL PLL at ff760040: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... SPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz SPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz SPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz SPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz U-Boot SPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17 +0200) mmc@fe320000: Got clock clock-controller@ff760000 76 Trying to boot from MMC2 NOTICE: BL31: v2.6(debug): NOTICE: BL31: Built : 14:50:40, Jul 1 2022 INFO: GICv3 with legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 287 INFO: plat_rockchip_pmu_init(1624): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing! INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 Clearly the assertion is wrong at least for this PLL because the system boots with the assertion disarmed. Then again, it is not clear that the PLL is operated at this frequency at all - it is immediately changed to higher frequency when the memory type is detected. What would be a resonable way to make rk3399 bootable with clock debug enabled? Thanks Michal