diff for duplicates of <20220819140250.3892995-1-ajones@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index d7591f7..f306dc7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -17,7 +17,7 @@ I do suggest we apply this to the Svinal support [1] as we won't want to frustrate the compiler's inlining efforts with hard coded register selection. -[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/ +[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/ Andrew Jones (4): riscv: Add X register names to gpr-nums @@ -35,3 +35,9 @@ Andrew Jones (4): -- 2.37.1 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index c59be15..076c911 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,15 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH 0/4] riscv: Introduce support for defining instructions\0" "Date\0Fri, 19 Aug 2022 16:02:46 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + " kvm-riscv@lists.infradead.org\0" + "Cc\0linux-kernel@vger.kernel.org" + paul.walmsley@sifive.com + palmer@dabbelt.com + aou@eecs.berkeley.edu + anup@brainfault.org + mchitale@ventanamicro.com + " heiko@sntech.de\0" "\00:1\0" "b\0" "When compiling with toolchains that haven't yet been taught about\n" @@ -23,7 +31,7 @@ "want to frustrate the compiler's inlining efforts with hard coded\n" "register selection.\n" "\n" - "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/\n" + "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/\n" "\n" "Andrew Jones (4):\n" " riscv: Add X register names to gpr-nums\n" @@ -40,6 +48,12 @@ " create mode 100644 arch/riscv/include/asm/insn-def.h\n" "\n" "-- \n" - 2.37.1 + "2.37.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -d2c656f38d0cd6009c08e9f31436d0cb89aeaea77a958d34bd94445bb8987ddb +266676559bec0bf2e6b1f34c5d73d41a2dadfa2a24ab1d067929de5a99933ac7
diff --git a/a/1.txt b/N2/1.txt index d7591f7..dd97e19 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -17,7 +17,7 @@ I do suggest we apply this to the Svinal support [1] as we won't want to frustrate the compiler's inlining efforts with hard coded register selection. -[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/ +[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/ Andrew Jones (4): riscv: Add X register names to gpr-nums diff --git a/a/content_digest b/N2/content_digest index c59be15..604a787 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,7 +1,15 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH 0/4] riscv: Introduce support for defining instructions\0" "Date\0Fri, 19 Aug 2022 16:02:46 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + " kvm-riscv@lists.infradead.org\0" + "Cc\0linux-kernel@vger.kernel.org" + paul.walmsley@sifive.com + palmer@dabbelt.com + aou@eecs.berkeley.edu + anup@brainfault.org + mchitale@ventanamicro.com + " heiko@sntech.de\0" "\00:1\0" "b\0" "When compiling with toolchains that haven't yet been taught about\n" @@ -23,7 +31,7 @@ "want to frustrate the compiler's inlining efforts with hard coded\n" "register selection.\n" "\n" - "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/\n" + "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/\n" "\n" "Andrew Jones (4):\n" " riscv: Add X register names to gpr-nums\n" @@ -42,4 +50,4 @@ "-- \n" 2.37.1 -d2c656f38d0cd6009c08e9f31436d0cb89aeaea77a958d34bd94445bb8987ddb +3867dc323486b3a56580df18030cd4eada01add5c9ba7cedf3fdbdf7d811f0c6
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.