From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: linux-usb@vger.kernel.org
Cc: Yehezkel Bernat <YehezkelShB@gmail.com>,
Michael Jamet <michael.jamet@intel.com>,
Lukas Wunner <lukas@wunner.de>,
Andreas Noever <andreas.noever@gmail.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH 3/4] thunderbolt: Add helpers to check if CL states are enabled on port
Date: Tue, 23 Aug 2022 13:53:51 +0300 [thread overview]
Message-ID: <20220823105352.56306-4-mika.westerberg@linux.intel.com> (raw)
In-Reply-To: <20220823105352.56306-1-mika.westerberg@linux.intel.com>
We will need these when enabling lane margining support.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/thunderbolt/switch.c | 23 +++++++++++++++++++++++
drivers/thunderbolt/tb.h | 7 +++++++
2 files changed, 30 insertions(+)
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index deefc92c7c60..6b90bacb622e 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -1335,6 +1335,29 @@ static int tb_port_clx_enable(struct tb_port *port, enum tb_clx clx)
return __tb_port_clx_set(port, clx, true);
}
+/**
+ * tb_port_is_clx_enabled() - Is given CL state enabled
+ * @port: USB4 port to check
+ * @clx: CL state to check
+ *
+ * Returns true if given CL state is enabled for @port.
+ */
+bool tb_port_is_clx_enabled(struct tb_port *port, enum tb_clx clx)
+{
+ u32 phy, mask = LANE_ADP_CS_1_CL0S_ENABLE | LANE_ADP_CS_1_CL1_ENABLE;
+ int ret;
+
+ if (!tb_port_clx_supported(port, clx))
+ return false;
+
+ ret = tb_port_read(port, &phy, TB_CFG_PORT,
+ port->cap_phy + LANE_ADP_CS_1, 1);
+ if (ret)
+ return false;
+
+ return (phy & mask) == mask;
+}
+
static int tb_port_start_lane_initialization(struct tb_port *port)
{
int ret;
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 8291cabd2e92..2154b59c39ec 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -1035,6 +1035,13 @@ void tb_port_lane_bonding_disable(struct tb_port *port);
int tb_port_wait_for_link_width(struct tb_port *port, int width,
int timeout_msec);
int tb_port_update_credits(struct tb_port *port);
+bool tb_port_is_clx_enabled(struct tb_port *port, enum tb_clx clx);
+
+static inline bool tb_port_are_clx_enabled(struct tb_port *port)
+{
+ return tb_port_is_clx_enabled(port, TB_CL1) ||
+ tb_port_is_clx_enabled(port, TB_CL2);
+}
int tb_switch_find_vse_cap(struct tb_switch *sw, enum tb_switch_vse_cap vsec);
int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap);
--
2.35.1
next prev parent reply other threads:[~2022-08-23 13:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-23 10:53 [PATCH 0/4] thunderbolt: Add support for receiver lane margining Mika Westerberg
2022-08-23 10:53 ` [PATCH 1/4] thunderbolt: Move tb_xdomain_parent() to tb.h Mika Westerberg
2022-08-23 10:53 ` [PATCH 2/4] thunderbolt: Move port CL state functions into correct place in switch.c Mika Westerberg
2022-08-23 10:53 ` Mika Westerberg [this message]
2022-08-23 14:02 ` [PATCH 3/4] thunderbolt: Add helpers to check if CL states are enabled on port Lukas Wunner
2022-08-24 8:33 ` Mika Westerberg
2022-08-23 10:53 ` [PATCH 4/4] thunderbolt: Add support for receiver lane margining Mika Westerberg
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