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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Cc: bjorn.andersson@linaro.org, bp@alien8.de, mchehab@kernel.org,
	james.morse@arm.com, rric@kernel.org,
	linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org, quic_tsoni@quicinc.com
Subject: Re: [PATCH v2 1/3] soc: qcom: llcc: Pass SoC specific EDAC register offsets to EDAC driver
Date: Tue, 23 Aug 2022 21:01:52 +0530	[thread overview]
Message-ID: <20220823153152.GA6371@thinkpad> (raw)
In-Reply-To: <396e6b2e-11d1-a11d-206a-cfd69f6cd358@quicinc.com>

On Mon, Aug 22, 2022 at 05:29:13PM +0530, Sai Prakash Ranjan wrote:
> Hi Mani,
> 
> On 8/12/2022 11:36 AM, Manivannan Sadhasivam wrote:
> > The LLCC EDAC register offsets varies between each SoCs. Until now, the
> > EDAC driver used the hardcoded register offsets. But this caused crash
> > on SM8450 SoC where the register offsets has been changed.
> > 
> > So to avoid this crash and also to make it easy to accomodate changes for
> > new SoCs, let's pass the SoC specific register offsets to the EDAC driver.
> > 
> > Currently, two set of offsets are used. One is SM8450 specific and another
> > one is common to all SoCs.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> <snip> ...
> 
> >   static const struct qcom_llcc_config sm8350_cfg = {
> > @@ -309,6 +370,7 @@ static const struct qcom_llcc_config sm8350_cfg = {
> >   	.size           = ARRAY_SIZE(sm8350_data),
> >   	.need_llcc_cfg	= true,
> >   	.reg_offset	= llcc_v1_2_reg_offset,
> > +	.edac_reg	= &common_edac_reg,
> >   };
> >   static const struct qcom_llcc_config sm8450_cfg = {
> > @@ -316,6 +378,7 @@ static const struct qcom_llcc_config sm8450_cfg = {
> >   	.size           = ARRAY_SIZE(sm8450_data),
> >   	.need_llcc_cfg	= true,
> >   	.reg_offset	= llcc_v21_reg_offset,
> > +	.edac_reg	= &sm8450_edac_reg,
> >   };
> > 
> 
> Can we have LLCC version specific register offsets instead of SoC specific similar to reg_offset callbacks?
> For SM8450, it would be llcc_v21_edac_reg and for others llcc_v1_2_edac_reg instead of common_edac_reg.
> common_edac_reg is very general and is not exactly common for all, its just common for SoCs with same LLCC.
> 

I thought about it but I was not sure if rest of the SoCs are using version
v1.2. I know that reg_offset uses v1.2 but I was skeptical and hence used the
SoC specific offsets.

Can you confirm if rest of the SoCs are using v1.2?

Thanks,
Mani

> Version based is more applicable as multiple SoCs might use same LLCC versions and would reduce SoC specific data
> which would be needed for every SoC in case some newer LLCC comes out. I know you could just call sm8450_edac_reg
> for lets say sm8550 or so on to reduce duplication but that won't look good.
> 
> 
> Thanks,
> Sai

-- 
மணிவண்ணன் சதாசிவம்

  reply	other threads:[~2022-08-23 17:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-12  6:05 [PATCH v2 0/3] Fix crash when using Qcom LLCC/EDAC drivers Manivannan Sadhasivam
2022-08-12  6:06 ` [PATCH v2 1/3] soc: qcom: llcc: Pass SoC specific EDAC register offsets to EDAC driver Manivannan Sadhasivam
2022-08-22 11:59   ` Sai Prakash Ranjan
2022-08-23 15:31     ` Manivannan Sadhasivam [this message]
2022-08-24  5:13       ` Sai Prakash Ranjan
2022-08-24 12:57         ` Manivannan Sadhasivam
2022-08-24 13:07           ` Sai Prakash Ranjan
2022-08-12  6:06 ` [PATCH v2 2/3] EDAC/qcom: Get rid of hardcoded register offsets Manivannan Sadhasivam
2022-08-12  6:06 ` [PATCH v2 3/3] MAINTAINERS: Add myself as the maintainer for qcom_edac driver Manivannan Sadhasivam
2022-08-22 11:43   ` Sai Prakash Ranjan
2022-10-26 12:38   ` Borislav Petkov

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