From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B7A1C6498F for ; Thu, 25 Aug 2022 01:39:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8B4BD0D37; Thu, 25 Aug 2022 01:38:19 +0000 (UTC) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC43BD0C9A; Thu, 25 Aug 2022 01:38:03 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8803061AF2; Thu, 25 Aug 2022 01:38:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5673BC433D6; Thu, 25 Aug 2022 01:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661391481; bh=CBbnhCg1r7UfbDv4vlNLCZTRgRNAqhTKzIzp++8xy9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P7rKZ7frNNKdXyrsZm6rO7TqZfcVslFi+UTar901cRX6G0+ZGebzoFSt2aoOd/MmW NLPBwv3TqSAhkpScV8bN0EO5wlXHRV6LXldSyp7DaXpEZVjXCnSIOOGby/D6rp9q5j vxCVy/hs82XTykV/fdz3tcxeHe1mej3EsfaYVZg9mUFdR5m4L92DarsnIVAj8GCV15 G7Ud6TSqQxVzdWoqOq2mn4cRUHFk6zmXWbLGjH+a08CzcdcS7npuCPS8rIFUD/Dnie p8Q7lqJyTst1W+s5LHkIDvljO8JfZOaqivsOckApAW/4eaE76pSPo9UhH1Kg9eXLEj 4fITTfid/5x3A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 5.15 12/20] drm/amd/display: Fix pixel clock programming Date: Wed, 24 Aug 2022 21:37:04 -0400 Message-Id: <20220825013713.22656-12-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825013713.22656-1-sashal@kernel.org> References: <20220825013713.22656-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: HaoPing.Liu@amd.com, Aric Cyr , airlied@linux.ie, dri-devel@lists.freedesktop.org, Sasha Levin , Brian Chang , Rodrigo.Siqueira@amd.com, amd-gfx@lists.freedesktop.org, alex.hung@amd.com, michael.strauss@amd.com, harry.wentland@amd.com, Ilya Bakoulin , Charlene.Liu@amd.com, sunpeng.li@amd.com, Daniel Wheeler , dillon.varone@amd.com, Hansen.Dsouza@amd.com, David.Galiffi@amd.com, Xinhui.Pan@amd.com, daniel@ffwll.ch, Alex Deucher , christian.koenig@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Ilya Bakoulin [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] [Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 054823d12403..5f1b735da506 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -545,9 +545,11 @@ static void dce112_get_pix_clk_dividers_helper ( switch (pix_clk_params->color_depth) { case COLOR_DEPTH_101010: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_121212: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_161616: actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 845D0C3F6B0 for ; Thu, 25 Aug 2022 01:41:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234548AbiHYBlq (ORCPT ); Wed, 24 Aug 2022 21:41:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234935AbiHYBkn (ORCPT ); Wed, 24 Aug 2022 21:40:43 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7390B9C1CA; Wed, 24 Aug 2022 18:38:32 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 486FBB824CF; Thu, 25 Aug 2022 01:38:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5673BC433D6; Thu, 25 Aug 2022 01:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661391481; bh=CBbnhCg1r7UfbDv4vlNLCZTRgRNAqhTKzIzp++8xy9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P7rKZ7frNNKdXyrsZm6rO7TqZfcVslFi+UTar901cRX6G0+ZGebzoFSt2aoOd/MmW NLPBwv3TqSAhkpScV8bN0EO5wlXHRV6LXldSyp7DaXpEZVjXCnSIOOGby/D6rp9q5j vxCVy/hs82XTykV/fdz3tcxeHe1mej3EsfaYVZg9mUFdR5m4L92DarsnIVAj8GCV15 G7Ud6TSqQxVzdWoqOq2mn4cRUHFk6zmXWbLGjH+a08CzcdcS7npuCPS8rIFUD/Dnie p8Q7lqJyTst1W+s5LHkIDvljO8JfZOaqivsOckApAW/4eaE76pSPo9UhH1Kg9eXLEj 4fITTfid/5x3A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ilya Bakoulin , Aric Cyr , Brian Chang , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie, daniel@ffwll.ch, HaoPing.Liu@amd.com, Hansen.Dsouza@amd.com, Charlene.Liu@amd.com, dillon.varone@amd.com, David.Galiffi@amd.com, michael.strauss@amd.com, alex.hung@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.15 12/20] drm/amd/display: Fix pixel clock programming Date: Wed, 24 Aug 2022 21:37:04 -0400 Message-Id: <20220825013713.22656-12-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825013713.22656-1-sashal@kernel.org> References: <20220825013713.22656-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ilya Bakoulin [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] [Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 054823d12403..5f1b735da506 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -545,9 +545,11 @@ static void dce112_get_pix_clk_dividers_helper ( switch (pix_clk_params->color_depth) { case COLOR_DEPTH_101010: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_121212: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_161616: actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CFFAC6498F for ; Thu, 25 Aug 2022 01:39:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BDBED0D85; Thu, 25 Aug 2022 01:38:26 +0000 (UTC) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC43BD0C9A; Thu, 25 Aug 2022 01:38:03 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8803061AF2; Thu, 25 Aug 2022 01:38:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5673BC433D6; Thu, 25 Aug 2022 01:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661391481; bh=CBbnhCg1r7UfbDv4vlNLCZTRgRNAqhTKzIzp++8xy9o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P7rKZ7frNNKdXyrsZm6rO7TqZfcVslFi+UTar901cRX6G0+ZGebzoFSt2aoOd/MmW NLPBwv3TqSAhkpScV8bN0EO5wlXHRV6LXldSyp7DaXpEZVjXCnSIOOGby/D6rp9q5j vxCVy/hs82XTykV/fdz3tcxeHe1mej3EsfaYVZg9mUFdR5m4L92DarsnIVAj8GCV15 G7Ud6TSqQxVzdWoqOq2mn4cRUHFk6zmXWbLGjH+a08CzcdcS7npuCPS8rIFUD/Dnie p8Q7lqJyTst1W+s5LHkIDvljO8JfZOaqivsOckApAW/4eaE76pSPo9UhH1Kg9eXLEj 4fITTfid/5x3A== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 5.15 12/20] drm/amd/display: Fix pixel clock programming Date: Wed, 24 Aug 2022 21:37:04 -0400 Message-Id: <20220825013713.22656-12-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825013713.22656-1-sashal@kernel.org> References: <20220825013713.22656-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: HaoPing.Liu@amd.com, airlied@linux.ie, dri-devel@lists.freedesktop.org, Sasha Levin , Brian Chang , Rodrigo.Siqueira@amd.com, amd-gfx@lists.freedesktop.org, alex.hung@amd.com, michael.strauss@amd.com, Ilya Bakoulin , Charlene.Liu@amd.com, sunpeng.li@amd.com, Daniel Wheeler , dillon.varone@amd.com, Hansen.Dsouza@amd.com, David.Galiffi@amd.com, Xinhui.Pan@amd.com, Alex Deucher , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ilya Bakoulin [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] [Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 054823d12403..5f1b735da506 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -545,9 +545,11 @@ static void dce112_get_pix_clk_dividers_helper ( switch (pix_clk_params->color_depth) { case COLOR_DEPTH_101010: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_121212: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_161616: actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; -- 2.35.1