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Date:   Fri, 26 Aug 2022 18:49:22 -0700
From:   Jakub Kicinski <kuba@kernel.org>
To:     David Thompson <davthompson@nvidia.com>
Cc:     <davem@davemloft.net>, <edumazet@google.com>, <pabeni@redhat.com>,
        <netdev@vger.kernel.org>, <cai.huoqing@linux.dev>, <brgl@bgdev.pl>,
        <limings@nvidia.com>, Asmaa Mnebhi <asmaa@nvidia.com>
Subject: Re: [PATCH net v1] mlxbf_gige: compute MDIO period based on i1clk
Message-ID: <20220826184922.030fccb3@kernel.org>
In-Reply-To: <20220826155916.12491-1-davthompson@nvidia.com>
References: <20220826155916.12491-1-davthompson@nvidia.com>
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On Fri, 26 Aug 2022 11:59:16 -0400 David Thompson wrote:
> This patch adds logic to compute the MDIO period based on
> the i1clk, and thereafter write the MDIO period into the YU
> MDIO config register. The i1clk resource from the ACPI table
> is used to provide addressing to YU bootrecord PLL registers.
> The values in these registers are used to compute MDIO period.
> If the i1clk resource is not present in the ACPI table, then
> the current default hardcorded value of 430Mhz is used.
> The i1clk clock value of 430MHz is only accurate for boards
> with BF2 mid bin and main bin SoCs. The BF2 high bin SoCs
> have i1clk = 500MHz, but can support a slower MDIO period.
> 
> Fixes: f92e1869d74e ("Add Mellanox BlueField Gigabit Ethernet driver")
> Reviewed-by: Asmaa Mnebhi <asmaa@nvidia.com>
> Signed-off-by: David Thompson <davthompson@nvidia.com>

Hm, why did you repost this?