From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60680ECAAD8 for ; Tue, 30 Aug 2022 18:09:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1B4F484870; Tue, 30 Aug 2022 20:09:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=londelec.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=londelec-com.20210112.gappssmtp.com header.i=@londelec-com.20210112.gappssmtp.com header.b="z3wxCox6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 970A684994; Tue, 30 Aug 2022 19:49:46 +0200 (CEST) Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 386958488D for ; Tue, 30 Aug 2022 19:49:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=londelec.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=alan@londelec.com Received: by mail-lj1-x22f.google.com with SMTP id x10so12168571ljq.4 for ; Tue, 30 Aug 2022 10:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=londelec-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc; bh=W9oKdODFwteNSLEf/LIIYcywH3bgY0oS/+q+Fo0mpAg=; b=z3wxCox6ny5rWDGjMC/JE7YvZ/LoK7B04s5Dt9Z1uOuZ81ACAFN9BhjXhu1e8PQR77 AX3lvVtRIRg3jW8ys3UR2w9z1Og2vpz6Lhhcn99xqYeigG4OhI64Xl55gqTjf6MGD2jK Qg8nCS1lg0ZZJKQNvYMoWBCpbKXAuo5iGvoaJ+oobAwjcZqI0MFFGnJez4tDnZ5iqoGR 1PrwN5VByMA/GXaiEgKL1V0kGXp6OLSm9ColAe6LoqdEwBkYmJfF3ATGxnqLwng4L26P wIyyK/QP6Tab6SGU8Ld/aqMKclzj86Y3I+sybiwlEJKOdanZ8RVAUjqmuNPGOxZ52VI3 6K1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc; bh=W9oKdODFwteNSLEf/LIIYcywH3bgY0oS/+q+Fo0mpAg=; b=H4zf+btQ+FBE/HVPKCCLbA0V6dE8IaoQGBPPCs7uGAEcHilkWGrUfMYACNDTOPyexk OM0KA6vp1T8b00qcRpTAZYp5azhhSVKrHDK8OwHK4UuhXRcmRcJCuw6WwLznZPBSZuTA qjkLEuZS8PAvaRBWOrtX0yRP8e5Gxo3JoOYIPnKAFwUtCF6/YJJoSGM40XiDRhax8rBZ Mir81xmh5QDuRzm8AgHNQs+AWqGf7WzekoG7H3E1Ao4ojGla3ep6PCoH1M1qq2h93m8g KQv4HhgPRfWASv9BOXCugyyA7qcQGmUZs0Bdd6+wRbBGzad/itrlwLB91Fqdrbxv07Mk U7uA== X-Gm-Message-State: ACgBeo14MDCkAFTUt3hkSrlTLZprm4EFaB4vEcHq1XWABVYhcDAc4J3Z 9zIW5DQQ4ANnq27enCTluukmsw== X-Google-Smtp-Source: AA6agR4VS8wdUx/vfTiTgiFoUqGS9K2zEWM7D1g62nWL9AxE23+LZSgzFFjmSV5Fe63o/qmGCUkGQA== X-Received: by 2002:a2e:9c03:0:b0:262:9b6d:bcc0 with SMTP id s3-20020a2e9c03000000b002629b6dbcc0mr6091499lji.312.1661881783468; Tue, 30 Aug 2022 10:49:43 -0700 (PDT) Received: from localhost.localdomain ([81.198.7.171]) by smtp.gmail.com with ESMTPSA id a25-20020a056512201900b004946e056c4asm688423lfb.194.2022.08.30.10.49.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 10:49:43 -0700 (PDT) From: Alan Kay To: Stefano Babic Cc: Marek Vasut , Alan Kay , Fabio Estevam , "NXP i.MX U-Boot Team" , u-boot@lists.denx.de Subject: [RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V Date: Tue, 30 Aug 2022 18:49:32 +0100 Message-Id: <20220830174932.96360-1-alan@londelec.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 30 Aug 2022 20:09:32 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean mxs_power_enable_4p2() was added to mxs_batt_boot() in 'commit a0f97610757d ("ARM: mxs: Enable DCDC converter for battery boot")' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in mxs_power_enable_4p2() that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail e.g. setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); In case the mx28 is powered by the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails there is no issue. However if the mx28 is powered by the DCDC_BATT source only without 5V, disabling the DCDC converter outputs causes brownout power down. The proposed solution is not to call mxs_power_enable_4p2() at all if the mx28 is powered by the DCDC_BATT source only. There is no reason to enable 4P2 regulator in this case and setup of all registers is done in mxs_batt_boot(). Also there is no need to enable 5V brownout in mxs_power_init() in this case. Please consider if this is acceptable and I will submit a proper patch. Signed-off-by: Alan Kay --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..c8feadce54 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1267,7 +1269,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1