Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver

[Rob Herring <robh@kernel.org>]

On Tue, Aug 30, 2022 at 05:31:07AM +0000, Manne, Nava kishore wrote:
> Hi Krzysztof,
> 
> 	Please find my response inline.
> 
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Sent: Wednesday, August 24, 2022 6:29 PM
> > To: Manne, Nava kishore <nava.kishore.manne@amd.com>; git (AMD-Xilinx)
> > <git@amd.com>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> > michal.simek@xilinx.com; mdf@kernel.org; hao.wu@intel.com;
> > yilun.xu@intel.com; trix@redhat.com; p.zabel@pengutronix.de;
> > gregkh@linuxfoundation.org; ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> > abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> > lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> > linus.walleij@linaro.org; nava.manne@xilinx.com;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> > Subject: Re: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi
> > config driver
> > 
> > On 24/08/2022 06:55, Nava kishore Manne wrote:
> > > Xilinx Zynq US+ MPSoC platform connect the PS to the programmable
> > > logic(PL) through the AXI port. This AXI port helps to establish
> > 
> > Use subject prefixes matching the subsystem (git log --oneline -- ...).
> > 
> 
> Will fix in v2.

This is what we assume. No need to reply back with agreement, and save 
us some mail to read.

Rob