diff for duplicates of <20220831172500.752195-1-ajones@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index 863a2e2..7087a81 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -17,7 +17,7 @@ I do suggest we apply this to the Svinal support [1] as we won't want to frustrate the compiler's inlining efforts with hard coded register selection. -[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/ +[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/ v2: - Cleaned up some whitespace issues pointed out by Anup, myself @@ -41,3 +41,9 @@ Andrew Jones (4): -- 2.37.2 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index a783f36..35a95e0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,15 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v2 0/4] riscv: Introduce support for defining instructions\0" "Date\0Wed, 31 Aug 2022 19:24:56 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + " kvm-riscv@lists.infradead.org\0" + "Cc\0linux-kernel@vger.kernel.org" + paul.walmsley@sifive.com + palmer@dabbelt.com + aou@eecs.berkeley.edu + anup@brainfault.org + mchitale@ventanamicro.com + " heiko@sntech.de\0" "\00:1\0" "b\0" "When compiling with toolchains that haven't yet been taught about\n" @@ -23,7 +31,7 @@ "want to frustrate the compiler's inlining efforts with hard coded\n" "register selection.\n" "\n" - "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/\n" + "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/\n" "\n" "v2:\n" " - Cleaned up some whitespace issues pointed out by Anup, myself\n" @@ -46,6 +54,12 @@ " create mode 100644 arch/riscv/include/asm/insn-def.h\n" "\n" "-- \n" - 2.37.2 + "2.37.2\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -390fbba738e9ccac2d40a866ae84575dfe7b7aca62783105bef53fa3110a2889 +71ed58c87abff98b150703ec2241b63fc9cc52b2bad7a62777c3f59ddd64febe
diff --git a/a/1.txt b/N2/1.txt index 863a2e2..61c67db 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -17,7 +17,7 @@ I do suggest we apply this to the Svinal support [1] as we won't want to frustrate the compiler's inlining efforts with hard coded register selection. -[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/ +[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/ v2: - Cleaned up some whitespace issues pointed out by Anup, myself diff --git a/a/content_digest b/N2/content_digest index a783f36..ce394be 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,7 +1,15 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v2 0/4] riscv: Introduce support for defining instructions\0" "Date\0Wed, 31 Aug 2022 19:24:56 +0200\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + " kvm-riscv@lists.infradead.org\0" + "Cc\0linux-kernel@vger.kernel.org" + paul.walmsley@sifive.com + palmer@dabbelt.com + aou@eecs.berkeley.edu + anup@brainfault.org + mchitale@ventanamicro.com + " heiko@sntech.de\0" "\00:1\0" "b\0" "When compiling with toolchains that haven't yet been taught about\n" @@ -23,7 +31,7 @@ "want to frustrate the compiler's inlining efforts with hard coded\n" "register selection.\n" "\n" - "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale at ventanamicro.com/\n" + "[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/\n" "\n" "v2:\n" " - Cleaned up some whitespace issues pointed out by Anup, myself\n" @@ -48,4 +56,4 @@ "-- \n" 2.37.2 -390fbba738e9ccac2d40a866ae84575dfe7b7aca62783105bef53fa3110a2889 +7dca7f61fa99ff0353a0f52a7e855cb619ed78d769407397462e6ed02546ba52
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