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Wed, 14 Sep 2022 00:13:33 -0500 From: Wayne Lin To: Subject: [PATCH V3 14/47] drm/amd/display: SubVP pipe split case Date: Wed, 14 Sep 2022 13:10:13 +0800 Message-ID: <20220914051046.1131186-15-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220914051046.1131186-1-Wayne.Lin@amd.com> References: <20220914051046.1131186-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT077:EE_|SJ1PR12MB6122:EE_ X-MS-Office365-Filtering-Correlation-Id: 85e81feb-53ba-4705-a7bb-08da960ff5aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uLofFXoiC4/od1ekz0619ChSZLEWoMaXg5vC1cCuZ0bKzDChvLiAiIPS0HEIb55/jiJct0YTcPX77PokhgoK91MGxrT/TkZktmR5bIFelp3zBLJfNrEHKHghvRCA7UuebHEIpJ0uhX3XkZFHbdV1VjRH+FrCOTrvZQEv2lepz/PYNNq+ZcAplXP/pA5ya59R2kY+pl9472G3zX0SAViWiYMMzkp8nWe22FgWZyhCqNUBEdnSUNr0iWpWKbGVaRlIk7Mj6Jms8L0yWTUk7AfsJnYZTbsJ2rcSpXdSxfv/74eitwj5TyGRbeG9j48a/ZR6TXbHN70shf5hXHzHYWu09quI9F/ji6AdNlonUWBjqavXY7roSpXWOJhdA//CQgcXsEdqA8mKAUTcyfCGIBSfVwZ10fLbtvhSXxS4X/BHOBb8D3Qb2cnxXEcrhOSiDGmuc8m3xDZC/rWHyuZBRcckGiYM27zD2QKpeaCSvWU2TNuGi8t4Qk+brTI2xEfxAkLe+7+UatDhFs38y3Nw/OZ7IUr0ZNoY4mVzb9EllGgCZ9KU82mLMLSLGMXM6GPNBaIzguYNCFdEvE6GVVew6QbU3UKGYN89NxNhKBzLcbo7aDkAryfNad0qtiEWTeMamDuDbkF1bh9MS+QtzWCVxDwt5sfvlI3DgAZ44LorpJp3FRS8+jlqJ/rahz076zbk/s7IzOlb9AZTnzN4zqxcacrIR+LQlppRAArtDOFYmQoQtexN55NbsXUQQ4dhhx/PajrIBVuwUfh3YGrhyUDRQ1kS7vqO8J1Jlgfqid7oe1CM0WgRqCZy8tq7DdenN0CaD76w X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199015)(46966006)(36840700001)(40470700004)(8936002)(81166007)(356005)(5660300002)(82740400003)(2906002)(4326008)(8676002)(1076003)(36860700001)(2616005)(478600001)(70586007)(70206006)(40460700003)(6666004)(186003)(426003)(26005)(47076005)(82310400005)(7696005)(336012)(40480700001)(41300700001)(54906003)(6916009)(83380400001)(36756003)(86362001)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 05:14:11.5686 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85e81feb-53ba-4705-a7bb-08da960ff5aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6122 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, Nevenko Stupar , Alvin Lee , wayne.lin@amd.com, Jun Lei , Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Why and How] For SubVP pipe split case, pass in split index for main and phantom pipes to ensure that the P-State sequence will force P-State for all required pipes. Reviewed-by: Nevenko Stupar Reviewed-by: Jun Lei Acked-by: Wayne Lin Signed-off-by: Alvin Lee --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 29 ++++++++++++++++++- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 ++++--- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 18 ++++++++---- 3 files changed, 47 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index df5ad02fc4b3..f09a3ddcf30d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -674,12 +674,32 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc, pipe_data->pipe_config.subvp_data.processing_delay_lines = div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); + + /* TODO: Uncomment once FW headers are promoted + if (subvp_pipe->bottom_pipe) { + pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; + } else if (subvp_pipe->next_odm_pipe) { + pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; + } else { + pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; + } + */ + // Find phantom pipe index based on phantom stream for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; + /* TODO: Uncomment once FW headers are promoted + if (phantom_pipe->bottom_pipe) { + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->pipe_idx; + } else if (phantom_pipe->next_odm_pipe) { + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->pipe_idx; + } else { + pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; + } + */ break; } } @@ -724,7 +744,9 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, if (!pipe->stream) continue; - if (pipe->plane_state && !pipe->top_pipe && + /* For SubVP pipe count, only count the top most (ODM / MPC) pipe + */ + if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) subvp_pipes[subvp_count++] = pipe; } @@ -737,7 +759,12 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, if (!pipe->stream) continue; + /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. + * Any ODM or MPC splits being used in SubVP will be handled internally in + * populate_subvp_cmd_pipe_info + */ if (pipe->plane_state && pipe->stream->mall_stream_config.paired_stream && + !pipe->top_pipe && !pipe->prev_odm_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); } else if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_NONE) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 86ab3a71c67b..ab56f14d6247 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1906,10 +1906,13 @@ void dcn20_post_unlock_program_front_end( * can underflow due to HUBP_VTG_SEL programming if done in the regular front end * programming sequence). */ - if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { - if (dc->hwss.update_phantom_vp_position) - dc->hwss.update_phantom_vp_position(dc, context, pipe); - dcn20_program_pipe(dc, pipe, context); + while (pipe) { + if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { + if (dc->hwss.update_phantom_vp_position) + dc->hwss.update_phantom_vp_position(dc, context, pipe); + dcn20_program_pipe(dc, pipe, context); + } + pipe = pipe->bottom_pipe; } } } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 2b3ffa300f25..7ff7cd8b5c93 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1160,17 +1160,23 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, vba->VoltageLevel = *vlevel; } } else { - // only call dcn20_validate_apply_pipe_split_flags if we found a supported config - memset(split, 0, MAX_PIPES * sizeof(int)); - memset(merge, 0, MAX_PIPES * sizeof(bool)); - *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); - vba->VoltageLevel = *vlevel; - // Most populate phantom DLG params before programming hardware / timing for phantom pipe DC_FP_START(); dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); DC_FP_END(); + /* Call validate_apply_pipe_split flags after calling DML getters for + * phantom dlg params, or some of the VBA params indicating pipe split + * can be overwritten by the getters. + * + * When setting up SubVP config, all pipes are merged before attempting to + * add phantom pipes. If pipe split (ODM / MPC) is required, both the main + * and phantom pipes will be split in the regular pipe splitting sequence. + */ + memset(split, 0, MAX_PIPES * sizeof(int)); + memset(merge, 0, MAX_PIPES * sizeof(bool)); + *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); + vba->VoltageLevel = *vlevel; // Note: We can't apply the phantom pipes to hardware at this time. We have to wait // until driver has acquired the DMCUB lock to do it safely. } -- 2.37.3