From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Chris Park <chris.park@amd.com>,
Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com,
agustin.gutierrez@amd.com, pavle.kotarac@amd.com
Subject: [PATCH V3 01/47] drm/amd/display: Port DCN30 420 logic to DCN32
Date: Wed, 14 Sep 2022 13:10:00 +0800 [thread overview]
Message-ID: <20220914051046.1131186-2-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20220914051046.1131186-1-Wayne.Lin@amd.com>
From: Chris Park <chris.park@amd.com>
[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine. If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.
[How]
FMT Buffer limit of 4096 in DCN32. Force ODM
combine depending on HActive and FMT Buffer limit.
Reject modes if TMDS 420 and above 4096.
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
---
.../dc/dml/dcn32/display_mode_vba_32.c | 2 ++
.../dc/dml/dcn32/display_mode_vba_util_32.c | 26 +++++++++++++++++++
.../dc/dml/dcn32/display_mode_vba_util_32.h | 1 +
3 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index ad100658132f..75be1e1ce543 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1992,6 +1992,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
dml32_CalculateODMMode(
mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
mode_lib->vba.HActive[k],
+ mode_lib->vba.OutputFormat[k],
mode_lib->vba.Output[k],
mode_lib->vba.ODMUse[k],
mode_lib->vba.MaxDispclk[i],
@@ -2014,6 +2015,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
dml32_CalculateODMMode(
mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,
mode_lib->vba.HActive[k],
+ mode_lib->vba.OutputFormat[k],
mode_lib->vba.Output[k],
mode_lib->vba.ODMUse[k],
mode_lib->vba.MaxDispclk[i],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 5b5b94f1024d..ad66e241f9ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -27,6 +27,8 @@
#include "display_mode_vba_32.h"
#include "../display_mode_lib.h"
+#define DCN32_MAX_FMT_420_BUFFER_WIDTH 4096
+
unsigned int dml32_dscceComputeDelay(
unsigned int bpc,
double BPP,
@@ -1179,6 +1181,7 @@ void dml32_CalculateDETBufferSize(
void dml32_CalculateODMMode(
unsigned int MaximumPixelsPerLinePerDSCUnit,
unsigned int HActive,
+ enum output_format_class OutFormat,
enum output_encoder_class Output,
enum odm_combine_policy ODMUse,
double StateDispclk,
@@ -1253,6 +1256,29 @@ void dml32_CalculateODMMode(
else
*TotalAvailablePipesSupport = false;
}
+ if (OutFormat == dm_420 && HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH &&
+ ODMUse != dm_odm_combine_policy_4to1) {
+ if (HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH * 4) {
+ *ODMMode = dm_odm_combine_mode_disabled;
+ *NumberOfDPP = 0;
+ *TotalAvailablePipesSupport = false;
+ } else if (HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH * 2 ||
+ *ODMMode == dm_odm_combine_mode_4to1) {
+ *ODMMode = dm_odm_combine_mode_4to1;
+ *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;
+ *NumberOfDPP = 4;
+ } else {
+ *ODMMode = dm_odm_combine_mode_2to1;
+ *RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;
+ *NumberOfDPP = 2;
+ }
+ }
+ if (Output == dm_hdmi && OutFormat == dm_420 &&
+ HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH) {
+ *ODMMode = dm_odm_combine_mode_disabled;
+ *NumberOfDPP = 0;
+ *TotalAvailablePipesSupport = false;
+ }
}
double dml32_CalculateRequiredDispclk(
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index 3dbc9cf46aad..55cead0d4237 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -216,6 +216,7 @@ void dml32_CalculateDETBufferSize(
void dml32_CalculateODMMode(
unsigned int MaximumPixelsPerLinePerDSCUnit,
unsigned int HActive,
+ enum output_format_class OutFormat,
enum output_encoder_class Output,
enum odm_combine_policy ODMUse,
double StateDispclk,
--
2.37.3
next prev parent reply other threads:[~2022-09-14 5:11 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 5:09 [PATCH V3 00/47] DC Patches September 14, 2022 Wayne Lin
2022-09-14 5:10 ` Wayne Lin [this message]
2022-09-14 5:10 ` [PATCH V3 02/47] drm/amd/display: Remove some unused definitions from DCN32/321 Wayne Lin
2022-09-14 5:10 ` [PATCH V3 03/47] drm/amd/display: Fix pipe split prediction Wayne Lin
2022-09-14 5:10 ` [PATCH V3 04/47] drm/amd/display: add debug option for dramclk_change_latency in apu Wayne Lin
2022-09-14 5:10 ` [PATCH V3 05/47] drm/amd/display: Various logs added Wayne Lin
2022-09-14 5:10 ` [PATCH V3 06/47] drm/amd/display: Only consider pixle rate div policy for DCN32+ Wayne Lin
2022-09-14 5:10 ` [PATCH V3 07/47] drm/amd/display: Fix double cursor on non-video RGB MPO Wayne Lin
2022-09-14 5:10 ` [PATCH V3 08/47] drm/amd/display: fix dcn315 memory channel count and width read Wayne Lin
2022-09-14 5:10 ` [PATCH V3 09/47] drm/amd/display: Assume an LTTPR is always present on fixed_vs links Wayne Lin
2022-09-14 5:10 ` [PATCH V3 10/47] drm/amd/display: rework recent update PHY state commit Wayne Lin
2022-09-14 5:10 ` [PATCH V3 11/47] drm/amd/display: support proper mst payload removal when link is not in mst mode in dc Wayne Lin
2022-09-14 5:10 ` [PATCH V3 12/47] drm/amd/display: For ODM seamless transition require AUTO mode Wayne Lin
2022-09-14 5:10 ` [PATCH V3 13/47] drm/amd/display: Add debug option for allocating extra way for cursor Wayne Lin
2022-09-14 5:10 ` [PATCH V3 14/47] drm/amd/display: SubVP pipe split case Wayne Lin
2022-09-14 5:10 ` [PATCH V3 15/47] drm/amd/display: Disable SubVP on driver disable Wayne Lin
2022-09-14 5:10 ` [PATCH V3 16/47] drm/amd/display: Fix SubVP way calculation Wayne Lin
2022-09-14 5:10 ` [PATCH V3 17/47] drm/amd/display: [FW Promotion] Release 0.0.134.0 Wayne Lin
2022-09-14 5:10 ` [PATCH V3 18/47] drm/amd/display: 3.2.203 Wayne Lin
2022-09-14 5:10 ` [PATCH V3 19/47] drm/amd/display: Refactor edp panel power sequencer(PPS) codes Wayne Lin
2022-09-14 5:10 ` [PATCH V3 20/47] drm/amd/display: update gamut remap if plane has changed Wayne Lin
2022-09-14 5:10 ` [PATCH V3 21/47] drm/amd/display: skip audio setup when audio stream is enabled Wayne Lin
2022-09-14 5:10 ` [PATCH V3 22/47] drm/amd/display: Uncomment SubVP pipe split assignment in driver Wayne Lin
2022-09-14 5:10 ` [PATCH V3 23/47] drm/amd/display: Fix urgent latency override for DCN32/DCN321 Wayne Lin
2022-09-14 5:10 ` [PATCH V3 24/47] drm/amd/display: correct hostvm flag Wayne Lin
2022-09-14 5:10 ` [PATCH V3 25/47] drm/amd/display: Added new DCN301 Asic Id Wayne Lin
2022-09-14 5:10 ` [PATCH V3 26/47] drm/amd/display: Removing 2 phys Wayne Lin
2022-09-14 5:10 ` [PATCH V3 27/47] drm/amd/display: Expose few dchubbub functions Wayne Lin
2022-09-14 5:10 ` [PATCH V3 28/47] drm/amd/display: Update dummy P-state search to use DCN32 DML Wayne Lin
2022-09-14 5:10 ` [PATCH V3 29/47] drm/amd/display: Display distortion after hotplug 5K tiled display Wayne Lin
2022-09-14 5:10 ` [PATCH V3 30/47] drm/amd/display: Fix DP MST timeslot issue when fallback happened Wayne Lin
2022-09-14 5:10 ` [PATCH V3 31/47] drm/amd/display: Don't allocate DET for phantom pipes Wayne Lin
2022-09-14 5:10 ` [PATCH V3 32/47] drm/amd/display: Ignore k1/k2 values for virtual signal Wayne Lin
2022-09-14 5:10 ` [PATCH V3 33/47] drm/amd/display: increase dcn315 pstate change latency Wayne Lin
2022-09-14 5:10 ` [PATCH V3 34/47] drm/amd/display: do not compare integers of different widths Wayne Lin
2022-09-14 5:10 ` [PATCH V3 35/47] drm/amd/display: Assume connectors are on single slot Wayne Lin
2022-09-14 5:10 ` [PATCH V3 36/47] drm/amd/display: Enable committing subvp config Wayne Lin
2022-09-14 5:10 ` [PATCH V3 37/47] drm/amd/display: Add shift and mask for ICH_RESET_AT_END_OF_LINE Wayne Lin
2022-09-14 5:10 ` [PATCH V3 38/47] drm/amd/display: Disable OTG WA for the plane_state NULL case on DCN314 Wayne Lin
2022-09-14 5:10 ` [PATCH V3 39/47] drm/amd/display: Modify DML to adjust Vstartup Position Wayne Lin
2022-09-14 5:10 ` [PATCH V3 40/47] drm/amd/display: Revise Sink device string ID Wayne Lin
2022-09-14 5:10 ` [PATCH V3 41/47] drm/amd/display: log vertical interrupt 1 for debug Wayne Lin
2022-09-14 5:10 ` [PATCH V3 42/47] drm/amd/display: Do second pass through DML for DET calculation Wayne Lin
2022-09-14 5:10 ` [PATCH V3 43/47] drm/amd/display: update dccg based on HW delta Wayne Lin
2022-09-14 5:10 ` [PATCH V3 44/47] drm/amd/display: solve regression in update phy state refactor Wayne Lin
2022-09-14 5:10 ` [PATCH V3 45/47] drm/amd/display: correct num_dsc based on HW cap Wayne Lin
2022-09-14 5:10 ` [PATCH V3 46/47] drm/amd/display: Fix failures of disabling primary plans Wayne Lin
2022-09-14 13:31 ` Michel Dänzer
2022-09-14 13:40 ` Michel Dänzer
2022-09-14 16:30 ` Alex Hung
2022-09-14 16:55 ` Michel Dänzer
2022-09-14 16:55 ` Michel Dänzer
2022-09-14 20:08 ` Alex Hung
2022-09-14 20:08 ` Alex Hung
2022-09-15 8:55 ` Michel Dänzer
2022-09-15 8:55 ` Michel Dänzer
2022-09-15 20:44 ` Rodrigo Siqueira Jordao
2022-09-16 9:12 ` Michel Dänzer
2022-09-14 5:10 ` [PATCH V3 47/47] drm/amd/display: 3.2.204 Wayne Lin
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