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Wed, 14 Sep 2022 00:12:31 -0500 From: Wayne Lin To: Subject: [PATCH V3 06/47] drm/amd/display: Only consider pixle rate div policy for DCN32+ Date: Wed, 14 Sep 2022 13:10:05 +0800 Message-ID: <20220914051046.1131186-7-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220914051046.1131186-1-Wayne.Lin@amd.com> References: <20220914051046.1131186-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT089:EE_|MN2PR12MB4472:EE_ X-MS-Office365-Filtering-Correlation-Id: b23996ad-c9da-4b19-e2e1-08da960fe080 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rX/u+1y/1Zi3V2xHOUjzvVXbxnQRLBU2gCjxCu4CRgwoz8ixzpKJLfxcxmllvhn92yypMWYU6cHpnkA9mrLQRPLo5/N+JF1S1vu9LKLPxLtClRkwyT6y4BW6/AauvAPTBFEvzZKtMbn3KwENUg6ZZgQKjISynEAng23o69UF1PriSXPM2WslkV4/sFnkhRzpK36Mc76Zx3kRMvtBent6Z+UftYPhlhRes6yLjSy2Mo+/n2J6MD+dXZUeBPnL1W3mxolhKwCB6toUQebHENjqyGI1zwph+RbojtdVGo75gmFa4lbvJhrBSJQ3UoKSE/YCJDCEyWVlsBsLGdOt5a/q9mPdZK512gp56CcRjy+AadlmTfH7MkZCEg8VleT3H+63GfRu5jL6GGke9Htp8rjYosalRPq1nbCKUm0vbxSJIKSk0SYXtA2J2aU7K3C2Bv48vxQ8bf/jOAZOIXiEFLBPNw6Te8Mcdeq7hGP0vE2xCB0eaz2CvIVxBhwzSkD5EO5OMjr1KiKWUxc47rP86FW6Hj2An/MyQrNhxWh4QpJdJxzpVaClpHqbIad2ojThoEomBys5UIuEwLxAkV99oc26FqGFKlTj1tpiBY5xyeOMMrI7ijMKX5Z+7TiK2C9Q1fzqlp7a8DvanNF9h7E48hPUuiyJ6ZyND1X5/w2KotKEcrF8TozGhjty3ESIYyuOi1e8j0JgrY0cplyAyyIv3Y9qe2NLXBfiSLTBM8huXdVHv+K3R43+R/wNfC8lVsqP2RsD46gGaPw/YPM5HSDVp6+A8VpicmFP/LzRokXCgH0QAJ7R40xn3zKYHoas3USN9+b5 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(376002)(346002)(396003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(6916009)(316002)(82310400005)(41300700001)(54906003)(70586007)(2616005)(7696005)(336012)(36756003)(40480700001)(4326008)(40460700003)(478600001)(186003)(70206006)(2906002)(6666004)(426003)(8936002)(356005)(5660300002)(86362001)(82740400003)(47076005)(1076003)(26005)(8676002)(81166007)(83380400001)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 05:13:35.9690 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b23996ad-c9da-4b19-e2e1-08da960fe080 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4472 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Martin Leung , Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com, Alvin Lee , wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Why and How] - Only consider pixel rate div policy for DCN32+ Reviewed-by: Martin Leung Acked-by: Wayne Lin Signed-off-by: Alvin Lee --- .../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 16 ++-------------- .../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 -- .../gpu/drm/amd/display/dc/dcn314/dcn314_init.c | 1 - 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c index 39931d48f385..f4d1b83979fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c @@ -343,7 +343,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig { struct dc_stream_state *stream = pipe_ctx->stream; unsigned int odm_combine_factor = 0; - struct dc *dc = pipe_ctx->stream->ctx->dc; bool two_pix_per_container = false; two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); @@ -364,7 +363,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig } else { *k1_div = PIXEL_RATE_DIV_BY_1; *k2_div = PIXEL_RATE_DIV_BY_4; - if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy) + if (odm_combine_factor == 2) *k2_div = PIXEL_RATE_DIV_BY_2; } } @@ -384,21 +383,10 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) return; odm_combine_factor = get_odm_config(pipe_ctx, NULL); - if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1 - || dcn314_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) + if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1) pix_per_cycle = 2; if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, pix_per_cycle); } - -bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) -{ - struct dc *dc = pipe_ctx->stream->ctx->dc; - - if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) && - dc->debug.enable_dp_dig_pixel_rate_div_policy) - return true; - return false; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h index d014580592ac..244280298212 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h @@ -41,6 +41,4 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx); -bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx); - #endif /* __DC_HWSS_DCN314_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c index fcf67eb3478f..72a563a4c3e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c @@ -146,7 +146,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values, .set_pixels_per_cycle = dcn314_set_pixels_per_cycle, - .is_dp_dig_pixel_rate_div_policy = dcn314_is_dp_dig_pixel_rate_div_policy, }; void dcn314_hw_sequencer_construct(struct dc *dc) -- 2.37.3