Re: [PATCH v3 2/3] cxl/acpi: Support CXL XOR Interleave Math (CXIMS)

[kernel test robot <lkp@intel.com>]

Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on 1cd8a2537eb07751d405ab7e2223f20338a90506]

url:    https://github.com/intel-lab-lkp/linux/commits/alison-schofield-intel-com/CXL-XOR-Interleave-Arithmetic/20220916-093308
base:   1cd8a2537eb07751d405ab7e2223f20338a90506
config: i386-randconfig-a013 (https://download.01.org/0day-ci/archive/20220916/202209161334.7i460KDI-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/52526703ddd3faa831e99eb2d778d5692aac43ee
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review alison-schofield-intel-com/CXL-XOR-Interleave-Arithmetic/20220916-093308
        git checkout 52526703ddd3faa831e99eb2d778d5692aac43ee
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/cxl/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/cxl/acpi.c:56:10: warning: shift count is negative [-Wshift-count-negative]
                   mask = GENMASK(51, eiw + ig);
                          ^~~~~~~~~~~~~~~~~~~~~
   include/linux/bits.h:38:31: note: expanded from macro 'GENMASK'
           (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
                                        ^~~~~~~~~~~~~~~
   include/linux/bits.h:36:11: note: expanded from macro '__GENMASK'
            (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
                    ^  ~~~~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +56 drivers/cxl/acpi.c

    16	
    17	/*
    18	 * Find a targets entry (n) in the host bridge interleave list.
    19	 * CXL Specfication 3.0 Table 9-22
    20	 */
    21	static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
    22	{
    23		struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
    24		struct cxims_data *cximsd = cxlrd->platform_data;
    25		struct cxl_decoder *cxld = &cxlsd->cxld;
    26		int ig = cxld->interleave_granularity;
    27		int iw = cxld->interleave_ways;
    28		int i, eiw, n = 0;
    29		u64 hpa, mask;
    30	
    31		if (dev_WARN_ONCE(&cxld->dev,
    32				  cxld->interleave_ways != cxlsd->nr_targets,
    33				  "misconfigured root decoder\n"))
    34			return NULL;
    35	
    36		if (iw == 1)
    37			/* Entry is always 0 for no interleave */
    38			return cxlrd->cxlsd.target[0];
    39	
    40		hpa = cxlrd->res->start + pos * ig;
    41	
    42		if (iw == 3) {
    43			/* Initialize 'i' for the modulo calc */
    44			i = 0;
    45			goto no_map;
    46		}
    47	
    48		/* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
    49		for (i = 0; i < cximsd->nr_maps; i++)
    50			n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
    51	
    52	no_map:
    53		/* IW: 3,6,12 add a modulo calculation to 'n' */
    54		if (!is_power_of_2(iw)) {
    55			eiw = ilog2(iw / 3) + 8;
  > 56			mask = GENMASK(51, eiw + ig);
    57			n |= (hpa & mask) % 3 << i;
    58		}
    59	
    60		return cxlrd->cxlsd.target[n];
    61	}
    62	

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