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[2a02:8440:6440:7fff:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id bj9-20020a0560001e0900b002365cd93d05sm3594512wrb.102.2022.11.04.07.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 07:14:12 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 04 Nov 2022 15:09:49 +0100 Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220919-v3-3-a803f2660127@baylibre.com> References: <20220919-v3-0-a803f2660127@baylibre.com> In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com> To: Rob Herring , Chun-Kuang Hu , Chunfeng Yun , Jitao shi , Matthias Brugger , Vinod Koul , CK Hu , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Philipp Zabel , Kishon Vijay Abraham I Cc: Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Guillaume Ranquet , mac.shen@mediatek.com, linux-phy@lists.infradead.org X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_071414_901957_319132BC X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org To prepare support for newer chips that need to share their address range with a dedicated ddc driver, use a regmap. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++-------------------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 4c80b6896dc3..9b02b30a193a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -171,7 +171,7 @@ struct mtk_hdmi { u32 ibias_up; struct regmap *sys_regmap; unsigned int sys_offset; - void __iomem *regs; + struct regmap *regs; enum hdmi_colorspace csp; struct hdmi_audio_param aud_param; bool audio_enable; @@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) return container_of(b, struct mtk_hdmi, bridge); } -static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) +static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val) { - return readl(hdmi->regs + offset); + return regmap_read(hdmi->regs, offset, val); } static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) { - writel(val, hdmi->regs + offset); + regmap_write(hdmi->regs, offset, val); } static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); + regmap_clear_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); + regmap_set_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); + regmap_update_bits(hdmi->regs, offset, mask, val); } static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) @@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG0); + mtk_hdmi_read(hdmi, GRL_CFG0, &val); val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); switch (i2s_fmt) { @@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG1); + mtk_hdmi_read(hdmi, GRL_CFG1, &val); if (input_type == HDMI_AUD_INPUT_I2S && (val & CFG1_SPDIF) == CFG1_SPDIF) { val &= ~CFG1_SPDIF; @@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); if (val & MIX_CTRL_SRC_EN) { val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); @@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); @@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG5); + mtk_hdmi_read(hdmi, GRL_CFG5, &val); val &= CFG5_CD_RATIO_MASK; switch (mclk) { @@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct device_node *cec_np, *remote, *i2c_np; struct platform_device *cec_pdev; struct regmap *regmap; - struct resource *mem; int ret; ret = mtk_hdmi_get_all_clk(hdmi, np); @@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } hdmi->sys_regmap = regmap; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, mem); + hdmi->regs = device_node_to_regmap(dev->of_node); if (IS_ERR(hdmi->regs)) { ret = PTR_ERR(hdmi->regs); goto put_device; -- b4 0.11.0-dev From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BE36C43217 for ; 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[2a02:8440:6440:7fff:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id bj9-20020a0560001e0900b002365cd93d05sm3594512wrb.102.2022.11.04.07.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 07:14:12 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 04 Nov 2022 15:09:49 +0100 Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem MIME-Version: 1.0 Message-Id: <20220919-v3-3-a803f2660127@baylibre.com> References: <20220919-v3-0-a803f2660127@baylibre.com> In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com> To: Rob Herring , Chun-Kuang Hu , Chunfeng Yun , Jitao shi , Matthias Brugger , Vinod Koul , CK Hu , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Philipp Zabel , Kishon Vijay Abraham I Cc: Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, AngeloGioacchino Del Regno , linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Guillaume Ranquet , mac.shen@mediatek.com, linux-phy@lists.infradead.org X-Mailer: b4 0.11.0-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_071414_034136_FE83D3CE X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org To prepare support for newer chips that need to share their address range with a dedicated ddc driver, use a regmap. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++-------------------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 4c80b6896dc3..9b02b30a193a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -171,7 +171,7 @@ struct mtk_hdmi { u32 ibias_up; struct regmap *sys_regmap; unsigned int sys_offset; - void __iomem *regs; + struct regmap *regs; enum hdmi_colorspace csp; struct hdmi_audio_param aud_param; bool audio_enable; @@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) return container_of(b, struct mtk_hdmi, bridge); } -static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) +static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val) { - return readl(hdmi->regs + offset); + return regmap_read(hdmi->regs, offset, val); } static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) { - writel(val, hdmi->regs + offset); + regmap_write(hdmi->regs, offset, val); } static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); + regmap_clear_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); + regmap_set_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); + regmap_update_bits(hdmi->regs, offset, mask, val); } static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) @@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG0); + mtk_hdmi_read(hdmi, GRL_CFG0, &val); val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); switch (i2s_fmt) { @@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG1); + mtk_hdmi_read(hdmi, GRL_CFG1, &val); if (input_type == HDMI_AUD_INPUT_I2S && (val & CFG1_SPDIF) == CFG1_SPDIF) { val &= ~CFG1_SPDIF; @@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); if (val & MIX_CTRL_SRC_EN) { val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); @@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); @@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG5); + mtk_hdmi_read(hdmi, GRL_CFG5, &val); val &= CFG5_CD_RATIO_MASK; switch (mclk) { @@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct device_node *cec_np, *remote, *i2c_np; struct platform_device *cec_pdev; struct regmap *regmap; - struct resource *mem; int ret; ret = mtk_hdmi_get_all_clk(hdmi, np); @@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } hdmi->sys_regmap = regmap; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, mem); + hdmi->regs = device_node_to_regmap(dev->of_node); if (IS_ERR(hdmi->regs)) { ret = PTR_ERR(hdmi->regs); goto put_device; -- b4 0.11.0-dev -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B95F4C433FE for ; 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Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++-------------------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 4c80b6896dc3..9b02b30a193a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -171,7 +171,7 @@ struct mtk_hdmi { u32 ibias_up; struct regmap *sys_regmap; unsigned int sys_offset; - void __iomem *regs; + struct regmap *regs; enum hdmi_colorspace csp; struct hdmi_audio_param aud_param; bool audio_enable; @@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) return container_of(b, struct mtk_hdmi, bridge); } -static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) +static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val) { - return readl(hdmi->regs + offset); + return regmap_read(hdmi->regs, offset, val); } static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) { - writel(val, hdmi->regs + offset); + regmap_write(hdmi->regs, offset, val); } static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); + regmap_clear_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); + regmap_set_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); + regmap_update_bits(hdmi->regs, offset, mask, val); } static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) @@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG0); + mtk_hdmi_read(hdmi, GRL_CFG0, &val); val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); switch (i2s_fmt) { @@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG1); + mtk_hdmi_read(hdmi, GRL_CFG1, &val); if (input_type == HDMI_AUD_INPUT_I2S && (val & CFG1_SPDIF) == CFG1_SPDIF) { val &= ~CFG1_SPDIF; @@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); if (val & MIX_CTRL_SRC_EN) { val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); @@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); @@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG5); + mtk_hdmi_read(hdmi, GRL_CFG5, &val); val &= CFG5_CD_RATIO_MASK; switch (mclk) { @@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct device_node *cec_np, *remote, *i2c_np; struct platform_device *cec_pdev; struct regmap *regmap; - struct resource *mem; int ret; ret = mtk_hdmi_get_all_clk(hdmi, np); @@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } hdmi->sys_regmap = regmap; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, mem); + hdmi->regs = device_node_to_regmap(dev->of_node); if (IS_ERR(hdmi->regs)) { ret = PTR_ERR(hdmi->regs); goto put_device; -- b4 0.11.0-dev _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 847EEC43219 for ; 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[2a02:8440:6440:7fff:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id bj9-20020a0560001e0900b002365cd93d05sm3594512wrb.102.2022.11.04.07.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 07:14:12 -0700 (PDT) From: Guillaume Ranquet Date: Fri, 04 Nov 2022 15:09:49 +0100 Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220919-v3-3-a803f2660127@baylibre.com> References: <20220919-v3-0-a803f2660127@baylibre.com> In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com> To: Rob Herring , Chun-Kuang Hu , Chunfeng Yun , Jitao shi , Matthias Brugger , Vinod Koul , CK Hu , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Philipp Zabel , Kishon Vijay Abraham I X-Mailer: b4 0.11.0-dev X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Guillaume Ranquet , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, mac.shen@mediatek.com, stuart.lee@mediatek.com, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To prepare support for newer chips that need to share their address range with a dedicated ddc driver, use a regmap. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++-------------------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 4c80b6896dc3..9b02b30a193a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -171,7 +171,7 @@ struct mtk_hdmi { u32 ibias_up; struct regmap *sys_regmap; unsigned int sys_offset; - void __iomem *regs; + struct regmap *regs; enum hdmi_colorspace csp; struct hdmi_audio_param aud_param; bool audio_enable; @@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) return container_of(b, struct mtk_hdmi, bridge); } -static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) +static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val) { - return readl(hdmi->regs + offset); + return regmap_read(hdmi->regs, offset, val); } static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) { - writel(val, hdmi->regs + offset); + regmap_write(hdmi->regs, offset, val); } static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp &= ~bits; - writel(tmp, reg); + regmap_clear_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp |= bits; - writel(tmp, reg); + regmap_set_bits(hdmi->regs, offset, bits); } static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) { - void __iomem *reg = hdmi->regs + offset; - u32 tmp; - - tmp = readl(reg); - tmp = (tmp & ~mask) | (val & mask); - writel(tmp, reg); + regmap_update_bits(hdmi->regs, offset, mask, val); } static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) @@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG0); + mtk_hdmi_read(hdmi, GRL_CFG0, &val); val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); switch (i2s_fmt) { @@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG1); + mtk_hdmi_read(hdmi, GRL_CFG1, &val); if (input_type == HDMI_AUD_INPUT_I2S && (val & CFG1_SPDIF) == CFG1_SPDIF) { val &= ~CFG1_SPDIF; @@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); if (val & MIX_CTRL_SRC_EN) { val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); @@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) { u32 val; - val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); + mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val); val &= ~MIX_CTRL_SRC_EN; mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); @@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, { u32 val; - val = mtk_hdmi_read(hdmi, GRL_CFG5); + mtk_hdmi_read(hdmi, GRL_CFG5, &val); val &= CFG5_CD_RATIO_MASK; switch (mclk) { @@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct device_node *cec_np, *remote, *i2c_np; struct platform_device *cec_pdev; struct regmap *regmap; - struct resource *mem; int ret; ret = mtk_hdmi_get_all_clk(hdmi, np); @@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, } hdmi->sys_regmap = regmap; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, mem); + hdmi->regs = device_node_to_regmap(dev->of_node); if (IS_ERR(hdmi->regs)) { ret = PTR_ERR(hdmi->regs); goto put_device; -- b4 0.11.0-dev