From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A831EC32771 for ; Mon, 26 Sep 2022 14:50:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PNqgty1xH7DVJqwDGknW8oUPQm1YwTSYu/qrFoWPnlQ=; b=1LbWXIYU4hhA9ihS4AJFzLJNU3 XRufIkEaFgrWkheOhvyP4sPiyJAltnAcyButf8TPGg+1MEdvn7FX3+v/E84rwV/qc9IRh967V42Wa +4oEWcUVIWV8CrEfnHTJnUarHEsQBEUO7dOSHG+r59Grne6tSrxN0DS2CBsMCIfWFdQny1RSrOQ4A SrBVzQ5nRf2CxF0ir/kVbupRBo9ZhHfo1fEOFWI7/yRD8OcHQPl5x0jtuGUf6AnP7vWZIlQEJDYwN BVChUtTyDOSup0533GdyK4TfI7P6xu07mq6OAeAA9Wbl76Ow9fqq/diMge75GUtUfZ8akaB/mUIjj Lj6NH+ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocpR5-005Urj-L0; Mon, 26 Sep 2022 14:50:19 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocpQu-005Upg-Dy; Mon, 26 Sep 2022 14:50:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E73EA60E16; Mon, 26 Sep 2022 14:50:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C27EBC433D6; Mon, 26 Sep 2022 14:50:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664203807; bh=89tkwdlJ8MMrAXQqIF+dkY5sEKAlYgkh9zDXoiDkyiA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=mBg4ovLme5zoarWLqRsVfgji0h8aLcgjg+qeNWjVKtqlDYk9Zj/9/4EcfIf3TKo9k 1eT4hBsLI9oriPXZQpnAl7ojVBPmKtClZRsDjVC2gJwkOja/xqjaNZW3rZLOEPQMFt LEZPQLnjjOaBvL3xpzmw3V2OJKtdkzLibk+OpvIBPllZkiVx/sKmj+7lJD1uXFanU1 eiCOneQotiQ/r57xLOb7PrQgrmeFDHCmq/oHtffaFXULbz4M/4sYrqsxriM1aY81V6 cUIVI3bcKnukmA2iuDCymz+M6fYJfJjtt82VoLIToby6+ZcEdGzm9+pg5aH4fjsYv+ dvXktc19ugF8Q== Date: Mon, 26 Sep 2022 20:19:57 +0530 From: Manivannan Sadhasivam To: Asutosh Das Cc: quic_nguyenb@quicinc.com, quic_xiaosenh@quicinc.com, quic_cang@quicinc.com, quic_nitirawa@quicinc.com, quic_rampraka@quicinc.com, quic_richardp@quicinc.com, stanley.chu@mediatek.com, adrian.hunter@intel.com, bvanassche@acm.org, avri.altman@wdc.com, beanhuo@micron.com, martin.petersen@oracle.com, linux-scsi@vger.kernel.org, Alim Akhtar , "James E.J. Bottomley" , Matthias Brugger , Krzysztof Kozlowski , open list , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/Mediatek SoC support" Subject: Re: [PATCH v1 04/16] ufs: core: mcq: Introduce Multi Circular Queue Message-ID: <20220926144957.GE101994@thinkpad> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_075008_569230_A3D7FF49 X-CRM114-Status: GOOD ( 35.26 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Thu, Sep 22, 2022 at 06:05:11PM -0700, Asutosh Das wrote: > Introduce multi-circular queue (MCQ) which has been added > in UFSHC v4.0 standard in addition to the Single Doorbell mode. > The MCQ mode supports multiple submission and completion queues. > Add support to configure the number of queues. > > Co-developed-by: Can Guo > Signed-off-by: Can Guo > Signed-off-by: Asutosh Das > --- > drivers/ufs/core/Makefile | 2 +- > drivers/ufs/core/ufs-mcq.c | 132 +++++++++++++++++++++++++++++++++++++++++ > drivers/ufs/core/ufshcd-priv.h | 1 + > drivers/ufs/core/ufshcd.c | 12 ++++ > include/ufs/ufshcd.h | 4 ++ > 5 files changed, 150 insertions(+), 1 deletion(-) > create mode 100644 drivers/ufs/core/ufs-mcq.c > > diff --git a/drivers/ufs/core/Makefile b/drivers/ufs/core/Makefile > index 62f38c5..4d02e0f 100644 > --- a/drivers/ufs/core/Makefile > +++ b/drivers/ufs/core/Makefile > @@ -1,7 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o > -ufshcd-core-y += ufshcd.o ufs-sysfs.o > +ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o > ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o > ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o > ufshcd-core-$(CONFIG_SCSI_UFS_CRYPTO) += ufshcd-crypto.o > diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c > new file mode 100644 > index 0000000..934556f > --- /dev/null > +++ b/drivers/ufs/core/ufs-mcq.c > @@ -0,0 +1,132 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center. All rights reserved. > + * > + * Authors: > + * Asutosh Das > + * Can Guo > + */ > + > +#include > +#include > +#include > +#include > +#include "ufshcd-priv.h" > + > +#define UFS_MCQ_MIN_RW_QUEUES 2 > +#define UFS_MCQ_MIN_READ_QUEUES 0 > +#define UFS_MCQ_MIN_POLL_QUEUES 0 > + > +static unsigned int dev_cmd_queue = 1; This looks like a constant, so consider switching to a macro. > + > +static int rw_queue_count_set(const char *val, const struct kernel_param *kp) > +{ > + unsigned int n; > + int ret; > + > + ret = kstrtouint(val, 10, &n); n is not used? While fixing, please use a better name. > + if (ret) > + return ret; Newline > + return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_RW_QUEUES, > + num_possible_cpus()); > +} > + > +static const struct kernel_param_ops rw_queue_count_ops = { > + .set = rw_queue_count_set, > + .get = param_get_uint, > +}; > + > +static unsigned int rw_queues; > +module_param_cb(rw_queues, &rw_queue_count_ops, &rw_queues, 0644); > +MODULE_PARM_DESC(rw_queues, > + "Number of interrupt driven I/O queues used for rw. Default value is nr_cpus"); > + > +static int read_queue_count_set(const char *val, const struct kernel_param *kp) > +{ > + unsigned int n; > + int ret; > + > + ret = kstrtouint(val, 10, &n); > + if (ret) > + return ret; Same as above > + return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_READ_QUEUES, > + num_possible_cpus()); > +} > + > +static const struct kernel_param_ops read_queue_count_ops = { > + .set = read_queue_count_set, > + .get = param_get_uint, > +}; > + > +static unsigned int read_queues; > +module_param_cb(read_queues, &read_queue_count_ops, &read_queues, 0644); > +MODULE_PARM_DESC(read_queues, > + "Number of interrupt driven read queues used for read. Default value is 0"); > + > +static int poll_queue_count_set(const char *val, const struct kernel_param *kp) > +{ > + unsigned int n; > + int ret; > + > + ret = kstrtouint(val, 10, &n); > + if (ret) > + return ret; Same as above > + return param_set_uint_minmax(val, kp, UFS_MCQ_MIN_POLL_QUEUES, > + num_possible_cpus()); > +} > + > +static const struct kernel_param_ops poll_queue_count_ops = { > + .set = poll_queue_count_set, > + .get = param_get_uint, > +}; > + > +static unsigned int poll_queues = 1; > +module_param_cb(poll_queues, &poll_queue_count_ops, &poll_queues, 0644); > +MODULE_PARM_DESC(poll_queues, > + "Number of poll queues used for r/w. Default value is 1"); > + > +static int ufshcd_mcq_config_nr_queues(struct ufs_hba *hba) > +{ > + int i, rem; > + u32 hbaq_cap, cmp, tot_queues; > + struct Scsi_Host *host = hba->host; > + > + hbaq_cap = hba->mcq_capabilities & 0xff; Define 0xff hbaq_cap should be named after the define used for 0xff. It is not quite understandable now. > + > + if (!rw_queues) > + rw_queues = num_possible_cpus(); > + > + tot_queues = dev_cmd_queue + read_queues + poll_queues + rw_queues; > + if (hbaq_cap < tot_queues) { > + dev_err(hba->dev, "Total queues (%d) exceeds HC capacity (%d)\n", > + tot_queues, hbaq_cap); > + return -EOPNOTSUPP; > + } > + > + rem = hbaq_cap - dev_cmd_queue; > + cmp = rem; > + hba->nr_queues[HCTX_TYPE_DEFAULT] = min3(cmp, rw_queues, > + num_possible_cpus()); > + rem -= hba->nr_queues[HCTX_TYPE_DEFAULT]; > + cmp = rem; > + hba->nr_queues[HCTX_TYPE_POLL] = min(cmp, poll_queues); Hmm, so the driver is not using the number of queues set by the user? If the number varies, I don't think it should be configurable. Thanks, Mani > + rem -= hba->nr_queues[HCTX_TYPE_POLL]; > + cmp = rem; > + hba->nr_queues[HCTX_TYPE_READ] = min(cmp, read_queues); > + > + for (i = 0; i < HCTX_MAX_TYPES; i++) > + host->nr_hw_queues += hba->nr_queues[i]; > + > + hba->nr_hw_queues = host->nr_hw_queues + dev_cmd_queue; > + return 0; > +} > + > +int ufshcd_mcq_init(struct ufs_hba *hba) > +{ > + int ret; > + > + ret = ufshcd_mcq_config_nr_queues(hba); > + > + return ret; > +} > + > diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h > index 8f67db2..cf6bdd8e 100644 > --- a/drivers/ufs/core/ufshcd-priv.h > +++ b/drivers/ufs/core/ufshcd-priv.h > @@ -50,6 +50,7 @@ int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, > int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, > enum flag_idn idn, u8 index, bool *flag_res); > void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); > +int ufshcd_mcq_init(struct ufs_hba *hba); > > #define SD_ASCII_STD true > #define SD_RAW false > diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c > index 426867b..f4bb402 100644 > --- a/drivers/ufs/core/ufshcd.c > +++ b/drivers/ufs/core/ufshcd.c > @@ -8172,6 +8172,15 @@ static int ufshcd_add_lus(struct ufs_hba *hba) > return ret; > } > > +static int ufshcd_config_mcq(struct ufs_hba *hba) > +{ > + int ret; > + > + ret = ufshcd_mcq_init(hba); > + > + return ret; > +} > + > /** > * ufshcd_probe_hba - probe hba to detect device and initialize it > * @hba: per-adapter instance > @@ -8221,6 +8230,9 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) > goto out; > > if (is_mcq_supported(hba)) { > + ret = ufshcd_config_mcq(hba); > + if (ret) > + goto out; > ret = scsi_add_host(host, hba->dev); > if (ret) { > dev_err(hba->dev, "scsi_add_host failed\n"); > diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h > index da7ec0c..298e103 100644 > --- a/include/ufs/ufshcd.h > +++ b/include/ufs/ufshcd.h > @@ -827,6 +827,8 @@ struct ufs_hba_monitor { > * ufshcd_resume_complete() > * @ext_iid_sup: is EXT_IID is supported by UFSHC > * @mcq_sup: is mcq supported by UFSHC > + * @nr_hw_queues: number of hardware queues configured > + * @nr_queues: number of Queues of different queue types > */ > struct ufs_hba { > void __iomem *mmio_base; > @@ -977,6 +979,8 @@ struct ufs_hba { > bool complete_put; > bool ext_iid_sup; > bool mcq_sup; > + unsigned int nr_hw_queues; > + unsigned int nr_queues[HCTX_MAX_TYPES]; > }; > > static inline bool is_mcq_supported(struct ufs_hba *hba) > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA67DC32771 for ; Mon, 26 Sep 2022 14:51:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q3nMtRRiWaPq6nC4OT4ygfqu99QCF3Yg0JrQEwIFT8o=; b=rApq0OkfgvC62l 8gz91gAQB56kO7V7+ORaYSsdVPfA+kKdb3lFzVM5j3EIHN58uiPdpgjlBgSjtGQ1w90OMLy3RNz+5 4kBE1je0GacrLMEIptOgTGl2u7QIAG2tDenHsCUGDJsTG13dsMDHDgciUjmPLn99hIZJ63C0RcR+v VY0SXkWIEda5HRcOOpE+hxENbUoAyPvHbo3nXKAjOkeA9j/sGscwRfiLuRZcml7w28wgN0N5NiJQo LVhZHT3fWhroG7palqLk3uudP75sC1jMJUhwWuEi1Ws78bxMhuHkBCO00guF1K6VzmyTQIbOVOY2U kq7408FY+vpzywSo/ZRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocpQy-005UrH-03; Mon, 26 Sep 2022 14:50:12 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocpQu-005Upg-Dy; Mon, 26 Sep 2022 14:50:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E73EA60E16; Mon, 26 Sep 2022 14:50:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C27EBC433D6; Mon, 26 Sep 2022 14:50:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664203807; bh=89tkwdlJ8MMrAXQqIF+dkY5sEKAlYgkh9zDXoiDkyiA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=mBg4ovLme5zoarWLqRsVfgji0h8aLcgjg+qeNWjVKtqlDYk9Zj/9/4EcfIf3TKo9k 1eT4hBsLI9oriPXZQpnAl7ojVBPmKtClZRsDjVC2gJwkOja/xqjaNZW3rZLOEPQMFt LEZPQLnjjOaBvL3xpzmw3V2OJKtdkzLibk+OpvIBPllZkiVx/sKmj+7lJD1uXFanU1 eiCOneQotiQ/r57xLOb7PrQgrmeFDHCmq/oHtffaFXULbz4M/4sYrqsxriM1aY81V6 cUIVI3bcKnukmA2iuDCymz+M6fYJfJjtt82VoLIToby6+ZcEdGzm9+pg5aH4fjsYv+ dvXktc19ugF8Q== Date: Mon, 26 Sep 2022 20:19:57 +0530 From: Manivannan Sadhasivam To: Asutosh Das Cc: quic_nguyenb@quicinc.com, quic_xiaosenh@quicinc.com, quic_cang@quicinc.com, quic_nitirawa@quicinc.com, quic_rampraka@quicinc.com, quic_richardp@quicinc.com, stanley.chu@mediatek.com, adrian.hunter@intel.com, bvanassche@acm.org, avri.altman@wdc.com, beanhuo@micron.com, martin.petersen@oracle.com, linux-scsi@vger.kernel.org, Alim Akhtar , "James E.J. Bottomley" , Matthias Brugger , Krzysztof Kozlowski , open list , "moderated list:ARM/Mediatek SoC support" , "moderated list:ARM/Mediatek SoC support" Subject: Re: [PATCH v1 04/16] ufs: core: mcq: Introduce Multi Circular Queue Message-ID: <20220926144957.GE101994@thinkpad> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_075008_569230_A3D7FF49 X-CRM114-Status: GOOD ( 35.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBTZXAgMjIsIDIwMjIgYXQgMDY6MDU6MTFQTSAtMDcwMCwgQXN1dG9zaCBEYXMgd3Jv dGU6Cj4gSW50cm9kdWNlIG11bHRpLWNpcmN1bGFyIHF1ZXVlIChNQ1EpIHdoaWNoIGhhcyBiZWVu IGFkZGVkCj4gaW4gVUZTSEMgdjQuMCBzdGFuZGFyZCBpbiBhZGRpdGlvbiB0byB0aGUgU2luZ2xl IERvb3JiZWxsIG1vZGUuCj4gVGhlIE1DUSBtb2RlIHN1cHBvcnRzIG11bHRpcGxlIHN1Ym1pc3Np b24gYW5kIGNvbXBsZXRpb24gcXVldWVzLgo+IEFkZCBzdXBwb3J0IHRvIGNvbmZpZ3VyZSB0aGUg bnVtYmVyIG9mIHF1ZXVlcy4KPiAKPiBDby1kZXZlbG9wZWQtYnk6IENhbiBHdW8gPHF1aWNfY2Fu Z0BxdWljaW5jLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBDYW4gR3VvIDxxdWljX2NhbmdAcXVpY2lu Yy5jb20+Cj4gU2lnbmVkLW9mZi1ieTogQXN1dG9zaCBEYXMgPHF1aWNfYXN1dG9zaGRAcXVpY2lu Yy5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvdWZzL2NvcmUvTWFrZWZpbGUgICAgICB8ICAgMiArLQo+ ICBkcml2ZXJzL3Vmcy9jb3JlL3Vmcy1tY3EuYyAgICAgfCAxMzIgKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysKPiAgZHJpdmVycy91ZnMvY29yZS91ZnNoY2QtcHJpdi5o IHwgICAxICsKPiAgZHJpdmVycy91ZnMvY29yZS91ZnNoY2QuYyAgICAgIHwgIDEyICsrKysKPiAg aW5jbHVkZS91ZnMvdWZzaGNkLmggICAgICAgICAgIHwgICA0ICsrCj4gIDUgZmlsZXMgY2hhbmdl ZCwgMTUwIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0 IGRyaXZlcnMvdWZzL2NvcmUvdWZzLW1jcS5jCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvdWZz L2NvcmUvTWFrZWZpbGUgYi9kcml2ZXJzL3Vmcy9jb3JlL01ha2VmaWxlCj4gaW5kZXggNjJmMzhj NS4uNGQwMmUwZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3Vmcy9jb3JlL01ha2VmaWxlCj4gKysr IGIvZHJpdmVycy91ZnMvY29yZS9NYWtlZmlsZQo+IEBAIC0xLDcgKzEsNyBAQAo+ICAjIFNQRFgt TGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gIAo+ICBvYmotJChDT05GSUdfU0NTSV9VRlNI Q0QpCQkrPSB1ZnNoY2QtY29yZS5vCj4gLXVmc2hjZC1jb3JlLXkJCQkJKz0gdWZzaGNkLm8gdWZz LXN5c2ZzLm8KPiArdWZzaGNkLWNvcmUteQkJCQkrPSB1ZnNoY2QubyB1ZnMtc3lzZnMubyB1ZnMt bWNxLm8KPiAgdWZzaGNkLWNvcmUtJChDT05GSUdfREVCVUdfRlMpCQkrPSB1ZnMtZGVidWdmcy5v Cj4gIHVmc2hjZC1jb3JlLSQoQ09ORklHX1NDU0lfVUZTX0JTRykJKz0gdWZzX2JzZy5vCj4gIHVm c2hjZC1jb3JlLSQoQ09ORklHX1NDU0lfVUZTX0NSWVBUTykJKz0gdWZzaGNkLWNyeXB0by5vCj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvdWZzL2NvcmUvdWZzLW1jcS5jIGIvZHJpdmVycy91ZnMvY29y ZS91ZnMtbWNxLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjkzNDU1 NmYKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy91ZnMvY29yZS91ZnMtbWNxLmMKPiBA QCAtMCwwICsxLDEzMiBAQAo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMC1v bmx5Cj4gKy8qCj4gKyAqIENvcHlyaWdodCAoYykgMjAyMiBRdWFsY29tbSBJbm5vdmF0aW9uIENl bnRlci4gQWxsIHJpZ2h0cyByZXNlcnZlZC4KPiArICoKPiArICogQXV0aG9yczoKPiArICoJQXN1 dG9zaCBEYXMgPHF1aWNfYXN1dG9zaGRAcXVpY2luYy5jb20+Cj4gKyAqCUNhbiBHdW8gPHF1aWNf Y2FuZ0BxdWljaW5jLmNvbT4KPiArICovCj4gKwo+ICsjaW5jbHVkZSA8YXNtL3VuYWxpZ25lZC5o Pgo+ICsjaW5jbHVkZSA8bGludXgvZG1hLW1hcHBpbmcuaD4KPiArI2luY2x1ZGUgPGxpbnV4L21v ZHVsZS5oPgo+ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+Cj4gKyNpbmNsdWRl ICJ1ZnNoY2QtcHJpdi5oIgo+ICsKPiArI2RlZmluZSBVRlNfTUNRX01JTl9SV19RVUVVRVMgMgo+ ICsjZGVmaW5lIFVGU19NQ1FfTUlOX1JFQURfUVVFVUVTIDAKPiArI2RlZmluZSBVRlNfTUNRX01J Tl9QT0xMX1FVRVVFUyAwCj4gKwo+ICtzdGF0aWMgdW5zaWduZWQgaW50IGRldl9jbWRfcXVldWUg PSAxOwoKVGhpcyBsb29rcyBsaWtlIGEgY29uc3RhbnQsIHNvIGNvbnNpZGVyIHN3aXRjaGluZyB0 byBhIG1hY3JvLgoKPiArCj4gK3N0YXRpYyBpbnQgcndfcXVldWVfY291bnRfc2V0KGNvbnN0IGNo YXIgKnZhbCwgY29uc3Qgc3RydWN0IGtlcm5lbF9wYXJhbSAqa3ApCj4gK3sKPiArCXVuc2lnbmVk IGludCBuOwo+ICsJaW50IHJldDsKPiArCj4gKwlyZXQgPSBrc3RydG91aW50KHZhbCwgMTAsICZu KTsKCm4gaXMgbm90IHVzZWQ/IFdoaWxlIGZpeGluZywgcGxlYXNlIHVzZSBhIGJldHRlciBuYW1l LgoKPiArCWlmIChyZXQpCj4gKwkJcmV0dXJuIHJldDsKCk5ld2xpbmUKCj4gKwlyZXR1cm4gcGFy YW1fc2V0X3VpbnRfbWlubWF4KHZhbCwga3AsIFVGU19NQ1FfTUlOX1JXX1FVRVVFUywKPiArCQkJ CSAgICAgbnVtX3Bvc3NpYmxlX2NwdXMoKSk7Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1 Y3Qga2VybmVsX3BhcmFtX29wcyByd19xdWV1ZV9jb3VudF9vcHMgPSB7Cj4gKwkuc2V0ID0gcndf cXVldWVfY291bnRfc2V0LAo+ICsJLmdldCA9IHBhcmFtX2dldF91aW50LAo+ICt9Owo+ICsKPiAr c3RhdGljIHVuc2lnbmVkIGludCByd19xdWV1ZXM7Cj4gK21vZHVsZV9wYXJhbV9jYihyd19xdWV1 ZXMsICZyd19xdWV1ZV9jb3VudF9vcHMsICZyd19xdWV1ZXMsIDA2NDQpOwo+ICtNT0RVTEVfUEFS TV9ERVNDKHJ3X3F1ZXVlcywKPiArCQkgIk51bWJlciBvZiBpbnRlcnJ1cHQgZHJpdmVuIEkvTyBx dWV1ZXMgdXNlZCBmb3IgcncuIERlZmF1bHQgdmFsdWUgaXMgbnJfY3B1cyIpOwo+ICsKPiArc3Rh dGljIGludCByZWFkX3F1ZXVlX2NvdW50X3NldChjb25zdCBjaGFyICp2YWwsIGNvbnN0IHN0cnVj dCBrZXJuZWxfcGFyYW0gKmtwKQo+ICt7Cj4gKwl1bnNpZ25lZCBpbnQgbjsKPiArCWludCByZXQ7 Cj4gKwo+ICsJcmV0ID0ga3N0cnRvdWludCh2YWwsIDEwLCAmbik7Cj4gKwlpZiAocmV0KQo+ICsJ CXJldHVybiByZXQ7CgpTYW1lIGFzIGFib3ZlCgo+ICsJcmV0dXJuIHBhcmFtX3NldF91aW50X21p bm1heCh2YWwsIGtwLCBVRlNfTUNRX01JTl9SRUFEX1FVRVVFUywKPiArCQkJCSAgICAgbnVtX3Bv c3NpYmxlX2NwdXMoKSk7Cj4gK30KPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qga2VybmVsX3Bh cmFtX29wcyByZWFkX3F1ZXVlX2NvdW50X29wcyA9IHsKPiArCS5zZXQgPSByZWFkX3F1ZXVlX2Nv dW50X3NldCwKPiArCS5nZXQgPSBwYXJhbV9nZXRfdWludCwKPiArfTsKPiArCj4gK3N0YXRpYyB1 bnNpZ25lZCBpbnQgcmVhZF9xdWV1ZXM7Cj4gK21vZHVsZV9wYXJhbV9jYihyZWFkX3F1ZXVlcywg JnJlYWRfcXVldWVfY291bnRfb3BzLCAmcmVhZF9xdWV1ZXMsIDA2NDQpOwo+ICtNT0RVTEVfUEFS TV9ERVNDKHJlYWRfcXVldWVzLAo+ICsJCSAiTnVtYmVyIG9mIGludGVycnVwdCBkcml2ZW4gcmVh ZCBxdWV1ZXMgdXNlZCBmb3IgcmVhZC4gRGVmYXVsdCB2YWx1ZSBpcyAwIik7Cj4gKwo+ICtzdGF0 aWMgaW50IHBvbGxfcXVldWVfY291bnRfc2V0KGNvbnN0IGNoYXIgKnZhbCwgY29uc3Qgc3RydWN0 IGtlcm5lbF9wYXJhbSAqa3ApCj4gK3sKPiArCXVuc2lnbmVkIGludCBuOwo+ICsJaW50IHJldDsK PiArCj4gKwlyZXQgPSBrc3RydG91aW50KHZhbCwgMTAsICZuKTsKPiArCWlmIChyZXQpCj4gKwkJ cmV0dXJuIHJldDsKClNhbWUgYXMgYWJvdmUKCj4gKwlyZXR1cm4gcGFyYW1fc2V0X3VpbnRfbWlu bWF4KHZhbCwga3AsIFVGU19NQ1FfTUlOX1BPTExfUVVFVUVTLAo+ICsJCQkJICAgICBudW1fcG9z c2libGVfY3B1cygpKTsKPiArfQo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBrZXJuZWxfcGFy YW1fb3BzIHBvbGxfcXVldWVfY291bnRfb3BzID0gewo+ICsJLnNldCA9IHBvbGxfcXVldWVfY291 bnRfc2V0LAo+ICsJLmdldCA9IHBhcmFtX2dldF91aW50LAo+ICt9Owo+ICsKPiArc3RhdGljIHVu c2lnbmVkIGludCBwb2xsX3F1ZXVlcyA9IDE7Cj4gK21vZHVsZV9wYXJhbV9jYihwb2xsX3F1ZXVl cywgJnBvbGxfcXVldWVfY291bnRfb3BzLCAmcG9sbF9xdWV1ZXMsIDA2NDQpOwo+ICtNT0RVTEVf UEFSTV9ERVNDKHBvbGxfcXVldWVzLAo+ICsJCSAiTnVtYmVyIG9mIHBvbGwgcXVldWVzIHVzZWQg Zm9yIHIvdy4gRGVmYXVsdCB2YWx1ZSBpcyAxIik7Cj4gKwo+ICtzdGF0aWMgaW50IHVmc2hjZF9t Y3FfY29uZmlnX25yX3F1ZXVlcyhzdHJ1Y3QgdWZzX2hiYSAqaGJhKQo+ICt7Cj4gKwlpbnQgaSwg cmVtOwo+ICsJdTMyIGhiYXFfY2FwLCBjbXAsIHRvdF9xdWV1ZXM7Cj4gKwlzdHJ1Y3QgU2NzaV9I b3N0ICpob3N0ID0gaGJhLT5ob3N0Owo+ICsKPiArCWhiYXFfY2FwID0gaGJhLT5tY3FfY2FwYWJp bGl0aWVzICYgMHhmZjsKCkRlZmluZSAweGZmCgpoYmFxX2NhcCBzaG91bGQgYmUgbmFtZWQgYWZ0 ZXIgdGhlIGRlZmluZSB1c2VkIGZvciAweGZmLiBJdCBpcyBub3QgcXVpdGUKdW5kZXJzdGFuZGFi bGUgbm93LgoKPiArCj4gKwlpZiAoIXJ3X3F1ZXVlcykKPiArCQlyd19xdWV1ZXMgPSBudW1fcG9z c2libGVfY3B1cygpOwo+ICsKPiArCXRvdF9xdWV1ZXMgPSBkZXZfY21kX3F1ZXVlICsgcmVhZF9x dWV1ZXMgKyBwb2xsX3F1ZXVlcyArIHJ3X3F1ZXVlczsKPiArCWlmIChoYmFxX2NhcCA8IHRvdF9x dWV1ZXMpIHsKPiArCQlkZXZfZXJyKGhiYS0+ZGV2LCAiVG90YWwgcXVldWVzICglZCkgZXhjZWVk cyBIQyBjYXBhY2l0eSAoJWQpXG4iLAo+ICsJCQl0b3RfcXVldWVzLCBoYmFxX2NhcCk7Cj4gKwkJ cmV0dXJuIC1FT1BOT1RTVVBQOwo+ICsJfQo+ICsKPiArCXJlbSA9IGhiYXFfY2FwIC0gZGV2X2Nt ZF9xdWV1ZTsKPiArCWNtcCA9IHJlbTsKPiArCWhiYS0+bnJfcXVldWVzW0hDVFhfVFlQRV9ERUZB VUxUXSA9IG1pbjMoY21wLCByd19xdWV1ZXMsCj4gKwkJCQkJCSBudW1fcG9zc2libGVfY3B1cygp KTsKPiArCXJlbSAtPSBoYmEtPm5yX3F1ZXVlc1tIQ1RYX1RZUEVfREVGQVVMVF07Cj4gKwljbXAg PSByZW07Cj4gKwloYmEtPm5yX3F1ZXVlc1tIQ1RYX1RZUEVfUE9MTF0gPSBtaW4oY21wLCBwb2xs X3F1ZXVlcyk7CgpIbW0sIHNvIHRoZSBkcml2ZXIgaXMgbm90IHVzaW5nIHRoZSBudW1iZXIgb2Yg cXVldWVzIHNldCBieSB0aGUgdXNlcj8KSWYgdGhlIG51bWJlciB2YXJpZXMsIEkgZG9uJ3QgdGhp bmsgaXQgc2hvdWxkIGJlIGNvbmZpZ3VyYWJsZS4KClRoYW5rcywKTWFuaQoKPiArCXJlbSAtPSBo YmEtPm5yX3F1ZXVlc1tIQ1RYX1RZUEVfUE9MTF07Cj4gKwljbXAgPSByZW07Cj4gKwloYmEtPm5y X3F1ZXVlc1tIQ1RYX1RZUEVfUkVBRF0gPSBtaW4oY21wLCByZWFkX3F1ZXVlcyk7Cj4gKwo+ICsJ Zm9yIChpID0gMDsgaSA8IEhDVFhfTUFYX1RZUEVTOyBpKyspCj4gKwkJaG9zdC0+bnJfaHdfcXVl dWVzICs9IGhiYS0+bnJfcXVldWVzW2ldOwo+ICsKPiArCWhiYS0+bnJfaHdfcXVldWVzID0gaG9z dC0+bnJfaHdfcXVldWVzICsgZGV2X2NtZF9xdWV1ZTsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ ICtpbnQgdWZzaGNkX21jcV9pbml0KHN0cnVjdCB1ZnNfaGJhICpoYmEpCj4gK3sKPiArCWludCBy ZXQ7Cj4gKwo+ICsJcmV0ID0gdWZzaGNkX21jcV9jb25maWdfbnJfcXVldWVzKGhiYSk7Cj4gKwo+ ICsJcmV0dXJuIHJldDsKPiArfQo+ICsKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy91ZnMvY29yZS91 ZnNoY2QtcHJpdi5oIGIvZHJpdmVycy91ZnMvY29yZS91ZnNoY2QtcHJpdi5oCj4gaW5kZXggOGY2 N2RiMi4uY2Y2YmRkOGUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy91ZnMvY29yZS91ZnNoY2QtcHJp di5oCj4gKysrIGIvZHJpdmVycy91ZnMvY29yZS91ZnNoY2QtcHJpdi5oCj4gQEAgLTUwLDYgKzUw LDcgQEAgaW50IHVmc2hjZF9xdWVyeV9hdHRyKHN0cnVjdCB1ZnNfaGJhICpoYmEsIGVudW0gcXVl cnlfb3Bjb2RlIG9wY29kZSwKPiAgaW50IHVmc2hjZF9xdWVyeV9mbGFnKHN0cnVjdCB1ZnNfaGJh ICpoYmEsIGVudW0gcXVlcnlfb3Bjb2RlIG9wY29kZSwKPiAgCWVudW0gZmxhZ19pZG4gaWRuLCB1 OCBpbmRleCwgYm9vbCAqZmxhZ19yZXMpOwo+ICB2b2lkIHVmc2hjZF9hdXRvX2hpYmVybjhfdXBk YXRlKHN0cnVjdCB1ZnNfaGJhICpoYmEsIHUzMiBhaGl0KTsKPiAraW50IHVmc2hjZF9tY3FfaW5p dChzdHJ1Y3QgdWZzX2hiYSAqaGJhKTsKPiAgCj4gICNkZWZpbmUgU0RfQVNDSUlfU1REIHRydWUK PiAgI2RlZmluZSBTRF9SQVcgZmFsc2UKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy91ZnMvY29yZS91 ZnNoY2QuYyBiL2RyaXZlcnMvdWZzL2NvcmUvdWZzaGNkLmMKPiBpbmRleCA0MjY4NjdiLi5mNGJi NDAyIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvdWZzL2NvcmUvdWZzaGNkLmMKPiArKysgYi9kcml2 ZXJzL3Vmcy9jb3JlL3Vmc2hjZC5jCj4gQEAgLTgxNzIsNiArODE3MiwxNSBAQCBzdGF0aWMgaW50 IHVmc2hjZF9hZGRfbHVzKHN0cnVjdCB1ZnNfaGJhICpoYmEpCj4gIAlyZXR1cm4gcmV0Owo+ICB9 Cj4gIAo+ICtzdGF0aWMgaW50IHVmc2hjZF9jb25maWdfbWNxKHN0cnVjdCB1ZnNfaGJhICpoYmEp Cj4gK3sKPiArCWludCByZXQ7Cj4gKwo+ICsJcmV0ID0gdWZzaGNkX21jcV9pbml0KGhiYSk7Cj4g Kwo+ICsJcmV0dXJuIHJldDsKPiArfQo+ICsKPiAgLyoqCj4gICAqIHVmc2hjZF9wcm9iZV9oYmEg LSBwcm9iZSBoYmEgdG8gZGV0ZWN0IGRldmljZSBhbmQgaW5pdGlhbGl6ZSBpdAo+ICAgKiBAaGJh OiBwZXItYWRhcHRlciBpbnN0YW5jZQo+IEBAIC04MjIxLDYgKzgyMzAsOSBAQCBzdGF0aWMgaW50 IHVmc2hjZF9wcm9iZV9oYmEoc3RydWN0IHVmc19oYmEgKmhiYSwgYm9vbCBpbml0X2Rldl9wYXJh bXMpCj4gIAkJCWdvdG8gb3V0Owo+ICAKPiAgCQlpZiAoaXNfbWNxX3N1cHBvcnRlZChoYmEpKSB7 Cj4gKwkJCXJldCA9IHVmc2hjZF9jb25maWdfbWNxKGhiYSk7Cj4gKwkJCWlmIChyZXQpCj4gKwkJ CQlnb3RvIG91dDsKPiAgCQkJcmV0ID0gc2NzaV9hZGRfaG9zdChob3N0LCBoYmEtPmRldik7Cj4g IAkJCWlmIChyZXQpIHsKPiAgCQkJCWRldl9lcnIoaGJhLT5kZXYsICJzY3NpX2FkZF9ob3N0IGZh aWxlZFxuIik7Cj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWZzL3Vmc2hjZC5oIGIvaW5jbHVkZS91 ZnMvdWZzaGNkLmgKPiBpbmRleCBkYTdlYzBjLi4yOThlMTAzIDEwMDY0NAo+IC0tLSBhL2luY2x1 ZGUvdWZzL3Vmc2hjZC5oCj4gKysrIGIvaW5jbHVkZS91ZnMvdWZzaGNkLmgKPiBAQCAtODI3LDYg KzgyNyw4IEBAIHN0cnVjdCB1ZnNfaGJhX21vbml0b3Igewo+ICAgKgl1ZnNoY2RfcmVzdW1lX2Nv bXBsZXRlKCkKPiAgICogQGV4dF9paWRfc3VwOiBpcyBFWFRfSUlEIGlzIHN1cHBvcnRlZCBieSBV RlNIQwo+ICAgKiBAbWNxX3N1cDogaXMgbWNxIHN1cHBvcnRlZCBieSBVRlNIQwo+ICsgKiBAbnJf aHdfcXVldWVzOiBudW1iZXIgb2YgaGFyZHdhcmUgcXVldWVzIGNvbmZpZ3VyZWQKPiArICogQG5y X3F1ZXVlczogbnVtYmVyIG9mIFF1ZXVlcyBvZiBkaWZmZXJlbnQgcXVldWUgdHlwZXMKPiAgICov Cj4gIHN0cnVjdCB1ZnNfaGJhIHsKPiAgCXZvaWQgX19pb21lbSAqbW1pb19iYXNlOwo+IEBAIC05 NzcsNiArOTc5LDggQEAgc3RydWN0IHVmc19oYmEgewo+ICAJYm9vbCBjb21wbGV0ZV9wdXQ7Cj4g IAlib29sIGV4dF9paWRfc3VwOwo+ICAJYm9vbCBtY3Ffc3VwOwo+ICsJdW5zaWduZWQgaW50IG5y X2h3X3F1ZXVlczsKPiArCXVuc2lnbmVkIGludCBucl9xdWV1ZXNbSENUWF9NQVhfVFlQRVNdOwo+ ICB9Owo+ICAKPiAgc3RhdGljIGlubGluZSBib29sIGlzX21jcV9zdXBwb3J0ZWQoc3RydWN0IHVm c19oYmEgKmhiYSkKPiAtLSAKPiAyLjcuNAo+IAoKLS0gCuCuruCuo+Cuv+CuteCuo+CvjeCuo+Cu qeCvjSDgrprgrqTgrr7grprgrr/grrXgrq7gr40KCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4 LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9y Zy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK