All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rob Herring <robh@kernel.org>
To: Frank Wunderlich <linux@fw-web.de>
Cc: linux-rockchip@lists.infradead.org,
	Frank Wunderlich <frank-w@public-files.de>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Yifeng Zhao <yifeng.zhao@rock-chips.com>,
	Johan Jonker <jbx6244@gmail.com>,
	Peter Geis <pgwipeout@gmail.com>, Simon Xue <xxm@rock-chips.com>,
	Liang Chen <cl@rock-chips.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy
Date: Tue, 4 Oct 2022 10:09:29 -0500	[thread overview]
Message-ID: <20221004150929.GA1506199-robh@kernel.org> (raw)
In-Reply-To: <20220825193836.54262-2-linux@fw-web.de>

On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> Add a new binding file for Rockchip PCIe v3 phy driver.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v4:
> - add reviewed-by
> - remove minitems for clock-names as i have static list to fix error
> - fix reg error by using 32-bit adressing in binding example
> - change lane-map to u32 data-lanes
> - tried to move data-lanes to phy-provider
>   https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
>   cloned and installed via pip install -e <local path>
>   verified with pip show, but phy-privider seems not to be applied
> 
> v3:
> - drop quotes
> - drop rk3588
> - make clockcount fixed to 3
> - full path for binding header file
> - drop phy-mode and its header and add lane-map
> 
> v2:
> dt-bindings: rename yaml for PCIe v3
> rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
> 
> changes in pcie3 phy yaml
> - change clock names to ordered const list
> - extend pcie30-phymode description
> - add phy-cells to required properties
> - drop unevaluatedProperties
> - example with 1 clock each line
> - use default property instead of text describing it
> - update license
> ---
>  .../bindings/phy/rockchip,pcie3-phy.yaml      | 80 +++++++++++++++++++
>  1 file changed, 80 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> new file mode 100644
> index 000000000000..9f2d8d2cc7a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PCIe v3 phy
> +
> +maintainers:
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,rk3568-pcie3-phy

The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix 
adding it here or removing from the driver. Are they not compatible with 
each other?

Rob

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Frank Wunderlich <linux@fw-web.de>
Cc: linux-rockchip@lists.infradead.org,
	Frank Wunderlich <frank-w@public-files.de>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Yifeng Zhao <yifeng.zhao@rock-chips.com>,
	Johan Jonker <jbx6244@gmail.com>,
	Peter Geis <pgwipeout@gmail.com>, Simon Xue <xxm@rock-chips.com>,
	Liang Chen <cl@rock-chips.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy
Date: Tue, 4 Oct 2022 10:09:29 -0500	[thread overview]
Message-ID: <20221004150929.GA1506199-robh@kernel.org> (raw)
In-Reply-To: <20220825193836.54262-2-linux@fw-web.de>

On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> Add a new binding file for Rockchip PCIe v3 phy driver.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v4:
> - add reviewed-by
> - remove minitems for clock-names as i have static list to fix error
> - fix reg error by using 32-bit adressing in binding example
> - change lane-map to u32 data-lanes
> - tried to move data-lanes to phy-provider
>   https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
>   cloned and installed via pip install -e <local path>
>   verified with pip show, but phy-privider seems not to be applied
> 
> v3:
> - drop quotes
> - drop rk3588
> - make clockcount fixed to 3
> - full path for binding header file
> - drop phy-mode and its header and add lane-map
> 
> v2:
> dt-bindings: rename yaml for PCIe v3
> rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
> 
> changes in pcie3 phy yaml
> - change clock names to ordered const list
> - extend pcie30-phymode description
> - add phy-cells to required properties
> - drop unevaluatedProperties
> - example with 1 clock each line
> - use default property instead of text describing it
> - update license
> ---
>  .../bindings/phy/rockchip,pcie3-phy.yaml      | 80 +++++++++++++++++++
>  1 file changed, 80 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> new file mode 100644
> index 000000000000..9f2d8d2cc7a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PCIe v3 phy
> +
> +maintainers:
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,rk3568-pcie3-phy

The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix 
adding it here or removing from the driver. Are they not compatible with 
each other?

Rob

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Frank Wunderlich <linux@fw-web.de>
Cc: linux-rockchip@lists.infradead.org,
	Frank Wunderlich <frank-w@public-files.de>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Yifeng Zhao <yifeng.zhao@rock-chips.com>,
	Johan Jonker <jbx6244@gmail.com>,
	Peter Geis <pgwipeout@gmail.com>, Simon Xue <xxm@rock-chips.com>,
	Liang Chen <cl@rock-chips.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy
Date: Tue, 4 Oct 2022 10:09:29 -0500	[thread overview]
Message-ID: <20221004150929.GA1506199-robh@kernel.org> (raw)
In-Reply-To: <20220825193836.54262-2-linux@fw-web.de>

On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> Add a new binding file for Rockchip PCIe v3 phy driver.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v4:
> - add reviewed-by
> - remove minitems for clock-names as i have static list to fix error
> - fix reg error by using 32-bit adressing in binding example
> - change lane-map to u32 data-lanes
> - tried to move data-lanes to phy-provider
>   https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
>   cloned and installed via pip install -e <local path>
>   verified with pip show, but phy-privider seems not to be applied
> 
> v3:
> - drop quotes
> - drop rk3588
> - make clockcount fixed to 3
> - full path for binding header file
> - drop phy-mode and its header and add lane-map
> 
> v2:
> dt-bindings: rename yaml for PCIe v3
> rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
> 
> changes in pcie3 phy yaml
> - change clock names to ordered const list
> - extend pcie30-phymode description
> - add phy-cells to required properties
> - drop unevaluatedProperties
> - example with 1 clock each line
> - use default property instead of text describing it
> - update license
> ---
>  .../bindings/phy/rockchip,pcie3-phy.yaml      | 80 +++++++++++++++++++
>  1 file changed, 80 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> new file mode 100644
> index 000000000000..9f2d8d2cc7a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PCIe v3 phy
> +
> +maintainers:
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,rk3568-pcie3-phy

The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix 
adding it here or removing from the driver. Are they not compatible with 
each other?

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Frank Wunderlich <linux@fw-web.de>
Cc: linux-rockchip@lists.infradead.org,
	Frank Wunderlich <frank-w@public-files.de>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Yifeng Zhao <yifeng.zhao@rock-chips.com>,
	Johan Jonker <jbx6244@gmail.com>,
	Peter Geis <pgwipeout@gmail.com>, Simon Xue <xxm@rock-chips.com>,
	Liang Chen <cl@rock-chips.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy
Date: Tue, 4 Oct 2022 10:09:29 -0500	[thread overview]
Message-ID: <20221004150929.GA1506199-robh@kernel.org> (raw)
In-Reply-To: <20220825193836.54262-2-linux@fw-web.de>

On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> Add a new binding file for Rockchip PCIe v3 phy driver.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v4:
> - add reviewed-by
> - remove minitems for clock-names as i have static list to fix error
> - fix reg error by using 32-bit adressing in binding example
> - change lane-map to u32 data-lanes
> - tried to move data-lanes to phy-provider
>   https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
>   cloned and installed via pip install -e <local path>
>   verified with pip show, but phy-privider seems not to be applied
> 
> v3:
> - drop quotes
> - drop rk3588
> - make clockcount fixed to 3
> - full path for binding header file
> - drop phy-mode and its header and add lane-map
> 
> v2:
> dt-bindings: rename yaml for PCIe v3
> rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
> 
> changes in pcie3 phy yaml
> - change clock names to ordered const list
> - extend pcie30-phymode description
> - add phy-cells to required properties
> - drop unevaluatedProperties
> - example with 1 clock each line
> - use default property instead of text describing it
> - update license
> ---
>  .../bindings/phy/rockchip,pcie3-phy.yaml      | 80 +++++++++++++++++++
>  1 file changed, 80 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> new file mode 100644
> index 000000000000..9f2d8d2cc7a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PCIe v3 phy
> +
> +maintainers:
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,rk3568-pcie3-phy

The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix 
adding it here or removing from the driver. Are they not compatible with 
each other?

Rob

  parent reply	other threads:[~2022-10-04 15:09 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-25 19:38 [PATCH v5 0/5] RK3568 PCIe V3 support Frank Wunderlich
2022-08-25 19:38 ` Frank Wunderlich
2022-08-25 19:38 ` Frank Wunderlich
2022-08-25 19:38 ` Frank Wunderlich
2022-08-25 19:38 ` [PATCH v5 1/5] dt-bindings: phy: rockchip: add PCIe v3 phy Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-09-04 15:06   ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-10-04 15:09   ` Rob Herring [this message]
2022-10-04 15:09     ` Rob Herring
2022-10-04 15:09     ` Rob Herring
2022-10-04 15:09     ` Rob Herring
2022-10-04 15:19     ` Frank Wunderlich
2022-10-04 15:19       ` Frank Wunderlich
2022-10-04 15:19       ` Frank Wunderlich
2022-10-04 15:19       ` Frank Wunderlich
2022-10-04 20:57       ` Sebastian Reichel
2022-10-04 20:57         ` Sebastian Reichel
2022-10-04 20:57         ` Sebastian Reichel
2022-10-04 20:57         ` Sebastian Reichel
2022-10-11  4:41         ` Andrew Powers-Holmes
2022-10-11  4:41           ` Andrew Powers-Holmes
2022-10-11  4:41           ` Andrew Powers-Holmes
2022-10-11  4:41           ` Andrew Powers-Holmes
2022-08-25 19:38 ` [PATCH v5 2/5] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38 ` [PATCH v5 3/5] phy: rockchip: Support PCIe v3 Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-09-04 15:06   ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-09-04 15:06     ` Vinod Koul
2022-08-25 19:38 ` [PATCH v5 4/5] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38 ` [PATCH v5 5/5] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-25 19:38   ` Frank Wunderlich
2022-08-26  6:50   ` Krzysztof Kozlowski
2022-08-26  6:50     ` Krzysztof Kozlowski
2022-08-26  6:50     ` Krzysztof Kozlowski
2022-08-26  6:50     ` Krzysztof Kozlowski
2022-08-27  8:50     ` Aw: " Frank Wunderlich
2022-08-27  8:50       ` Frank Wunderlich
2022-08-27  8:50       ` Frank Wunderlich
2022-08-27  8:50       ` Frank Wunderlich
2022-08-27  8:56       ` Krzysztof Kozlowski
2022-08-27  8:56         ` Krzysztof Kozlowski
2022-08-27  8:56         ` Krzysztof Kozlowski
2022-08-27  8:56         ` Krzysztof Kozlowski
2022-08-27  9:14         ` Aw: " Frank Wunderlich
2022-08-27  9:14           ` Frank Wunderlich
2022-08-27  9:14           ` Frank Wunderlich
2022-08-27  9:14           ` Frank Wunderlich
2022-08-27  9:19           ` Krzysztof Kozlowski
2022-08-27  9:19             ` Krzysztof Kozlowski
2022-08-27  9:19             ` Krzysztof Kozlowski
2022-08-27  9:19             ` Krzysztof Kozlowski
2022-09-04 15:28           ` Heiko Stübner
2022-09-04 15:28             ` Heiko Stübner
2022-09-04 15:28             ` Heiko Stübner
2022-09-04 15:28             ` Heiko Stübner
2022-09-04 17:22 ` (subset) [PATCH v5 0/5] RK3568 PCIe V3 support Heiko Stuebner
2022-09-04 17:22   ` Heiko Stuebner
2022-09-04 17:22   ` Heiko Stuebner
2022-09-04 17:22   ` Heiko Stuebner

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221004150929.GA1506199-robh@kernel.org \
    --to=robh@kernel.org \
    --cc=cl@rock-chips.com \
    --cc=devicetree@vger.kernel.org \
    --cc=frank-w@public-files.de \
    --cc=heiko@sntech.de \
    --cc=jbx6244@gmail.com \
    --cc=kishon@ti.com \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=krzysztof.kozlowski@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=linux@fw-web.de \
    --cc=p.zabel@pengutronix.de \
    --cc=pgwipeout@gmail.com \
    --cc=shawn.lin@rock-chips.com \
    --cc=vkoul@kernel.org \
    --cc=xxm@rock-chips.com \
    --cc=yifeng.zhao@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.