From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E26AC433FE for ; Fri, 14 Oct 2022 10:17:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4BDE684D99; Fri, 14 Oct 2022 12:17:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 99F0A84D99; Fri, 14 Oct 2022 12:17:28 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id A5BA784D57 for ; Fri, 14 Oct 2022 12:17:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=abdellatif.elkhlifi@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F4B713D5; Fri, 14 Oct 2022 03:17:31 -0700 (PDT) Received: from e121910.cambridge.arm.com (unknown [10.57.2.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 387093F67D; Fri, 14 Oct 2022 03:17:22 -0700 (PDT) Date: Fri, 14 Oct 2022 11:17:17 +0100 From: Abdellatif El Khlifi To: Jens Wiklander Cc: u-boot@lists.denx.de, nd@arm.com Subject: Re: [PATCH v5 02/10] arm64: smccc: clear the Xn registers after SMC calls Message-ID: <20221014101717.GA11420@e121910.cambridge.arm.com> References: <20220926101723.9965-1-abdellatif.elkhlifi@arm.com> <20220926140827.15125-1-abdellatif.elkhlifi@arm.com> <20220926140827.15125-3-abdellatif.elkhlifi@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, Sep 30, 2022 at 11:48:04AM +0200, Jens Wiklander wrote: > On Mon, Sep 26, 2022 at 03:08:19PM +0100, Abdellatif El Khlifi wrote: > > set to zero the x0-x17 registers > > > > As per the SMCCC v1.2 spec, unused result and scratch registers > > can leak information after an SMC call. We can mitigate against > > this risk by returning zero in each register. > > > > The leakage we are referring to is data leakage across exception > > levels. The intent is to prevent lower exception levels (EL1/EL0) > > from reading the SMC data exchanged at EL2. > > > > Signed-off-by: Abdellatif El Khlifi > > Cc: Tom Rini > > Cc: Simon Glass > > Cc: Ilias Apalodimas > > Cc: Jens Wiklander > > --- > > > > Changelog: > > =============== > > > > v4: > > > > * move the clearing code into a new macro: clear_gp_regs > > > > v3: > > > > * clear the Xn registers after SMC calls > > > > > > arch/arm/cpu/armv8/smccc-call.S | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S > > index ec6f299bc9..32f3eb8eeb 100644 > > --- a/arch/arm/cpu/armv8/smccc-call.S > > +++ b/arch/arm/cpu/armv8/smccc-call.S > > @@ -50,6 +50,12 @@ ENDPROC(__arm_smccc_hvc) > > > > #ifdef CONFIG_ARM64 > > > > + .macro clear_gp_regs > > + .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17 > > + mov x\n, xzr > > + .endr > > + .endm > > + > > .macro SMCCC_1_2 instr > > /* Save `res` and free a GPR that won't be clobbered */ > > stp x1, x19, [sp, #-16]! > > @@ -84,6 +90,9 @@ ENDPROC(__arm_smccc_hvc) > > stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] > > stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] > > > > + /* x0-x17 registers can leak information after an SMC or HVC call. Let's clear them */ > > + clear_gp_regs > > + > > This should in my opinion not be needed. The higher exception level should > only return what it indends to return and certainly not rely on lower > exception levels to try to hide eventual unintentionally revealed > secrets. > > In an earlier conversation you said: > > The leakage we are referring to is data leakage across exception levels. > > The intent is to prevent lower exception levels (EL1/EL0) to read the > > data exchanged at EL2. > > > > The linux kernel clears the general purpose registers before switching > > to EL0. As far as I know u-boot doesn't. > > > > So, the code above makes sure the registers are cleared. > > U-Boot is as far as I know not changing to EL0. Do you have a real example > where this cleaning actually would be needed? If it's needed I'd expect > the cleaning to be done just before changing exception level. No real example for that. But I tried to follow the spec as much as possible. Since, no real need for this I'm happy to remove the commit and this has been done in patchset v6. Thanks. > > Cheers, > Jens > > > /* Restore original x19 */ > > ldp xzr, x19, [sp], #16 > > ret > > -- > > 2.17.1 > >