Re: Fwd: [PATCH v2 06/17] ufs: core: mcq: Configure resource regions

[Asutosh Das <quic_asutoshd@quicinc.com>]

On Mon, Oct 17 2022 at 02:27 -0700, Eddie Huang wrote:
>Hi Can,
>
[...]

>Let me explain more detail about Mediatek UFS register assignment:
>a. 0x0 ~ 0x5FF: UFS common register
>b. 0x1600 ~   : MCQ register
>c. 0x2200: UFS common vendor specific register
>d. 0x2800: SQ/CQ head/tail pointer and interrupt status/enable register
>     0x2800 SQ0_head
>     0x2814 SQ0_IS
>     0x281C CQ0_head
>     0x2824 CQ0_IS
>
>The register location meet UFSHCI4.0 spec definition
>
>In legacy doorbell mode, need region a, c registers
>In MCQ mode, need region a, b, c, d registers
>
>As you can see, region b in the middle of region a and c. If I declare
>"mcq" in device tree, i.e.
>reg = <0, 0x11270000, 0, 0x2300>,
>      <0, 0x11271600, 0, 0x1400>;
>reg-names = "ufs_mem", "mcq";
>
>Linux kernel boot fail due to register region overlapped and
>devm_ioremap_resource() return error.
>
>If I don't declare "mcq" region in device tree, Linux kernel still boot
>fail due to ufshcd_mcq_config_resource() call devm_ioreamap_resource()
>using calculated res_mcq which is overlapped with ufs_mem.
>
>We treat UFS as a single IP, so we suggest:
>1. Map whole UFS register (include MCQ) in ufshcd_pltfrm_init()
>2. In ufshcd_mcq_config_resource() assign mcq_base address directly,
>ie,
>     hba->mcq_base = hba->mmio_base + MCQ_SQATTR_OFFSET(hba-
>>mcq_capabilities)
>3. In ufshcd_mcq_vops_op_runtime_config(), assign SQD, SQIS, CQD, CQIS
>base, offset and stride
>
>This is why I propose ufshcd_mcq_config_resource() to be customized,
>not in common code
How about we add a vops to ufshcd_mcq_config_resource().
SoC vendors should make sure that the vops populates the mcq_base.

>Regards,
>Eddie Huang
>
>