Re: [RFC PATCH v2 3/4] cxl: CXL Performance Monitoring Unit driver

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Thu, 22 Sep 2022 13:19:06 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> On 8/24/2022 3:36 AM, Jonathan Cameron wrote:
> > CXL rev 3.0 introduces a standard performance monitoring hardware
> > block to CXL. Instances are discovered using CXL Register Locator DVSEC
> > entries. Each CXL component may have multiple PMUs.
> >
> > This initial driver supports on a subset of types of counter.
> > It support counters that are either fixed or configurable, but requires
> > that they support the ability to freeze and write value whilst frozen.
> >
> > Development done with QEMU model which will be posted shortly.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>  
> Besides couple nits in comments below, Reviewed-by: Dave Jiang 
> <dave.jiang@intel.com>
Thanks,

> >> > +/*
> > + * Reset ensures no possibility of any information leaking to wrong
> > + * counter. Note that all fields written during start()
> > + */
> > +static void cpmu_reset_counter(struct cpmu_info *info, int idx)
> > +{
> > +	void __iomem *base = info->base;
> > +
> > +	/* Much of this register is read only */
> > +	writeq(0, base + CPMU_EVENT_CAP_REG(idx));
> > +	/* Filters are not per counter, so not reset here */  
> 
> s/not/no/

Good point. I went with 'so do not reset here'

I also did a scrub for consistent punctuation of those comments
that were full sentences.

> 
> DJ
> 
> > +	writeq(0, base + CPMU_COUNTER_REG(idx));
> > +}
> > +