From: Anup Patel <apatel@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH kvmtool 5/6] riscv: Add Zicbom extension support
Date: Tue, 18 Oct 2022 19:38:53 +0530 [thread overview]
Message-ID: <20221018140854.69846-6-apatel@ventanamicro.com> (raw)
In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com>
From: Andrew Jones <ajones@ventanamicro.com>
When the Zicbom extension is available expose it to the guest.
Also provide the guest the size of the cache block through DT.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
riscv/fdt.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/riscv/fdt.c b/riscv/fdt.c
index 8d6da11..30d3460 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -19,6 +19,7 @@ struct isa_ext_info isa_info_arr[] = {
{"sstc", KVM_RISCV_ISA_EXT_SSTC},
{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
+ {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
};
static void dump_fdt(const char *dtb_file, void *fdt)
@@ -44,6 +45,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
int cpu, pos, i, index, valid_isa_len;
const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG";
int arr_sz = ARRAY_SIZE(isa_info_arr);
+ unsigned long cbom_blksz = 0;
_FDT(fdt_begin_node(fdt, "cpus"));
_FDT(fdt_property_cell(fdt, "#address-cells", 0x1));
@@ -78,6 +80,13 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
/* This extension is not available in hardware */
continue;
+ if (isa_info_arr[i].ext_id == KVM_RISCV_ISA_EXT_ZICBOM && !cbom_blksz) {
+ reg.id = RISCV_CONFIG_REG(zicbom_block_size);
+ reg.addr = (unsigned long)&cbom_blksz;
+ if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0)
+ die("KVM_GET_ONE_REG failed (config.zicbom_block_size)");
+ }
+
if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) {
pr_warning("Insufficient space to append ISA exension\n");
break;
@@ -97,6 +106,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
_FDT(fdt_property_string(fdt, "mmu-type",
"riscv,sv32"));
_FDT(fdt_property_string(fdt, "riscv,isa", cpu_isa));
+ if (cbom_blksz)
+ _FDT(fdt_property_cell(fdt, "riscv,cbom-block-size", cbom_blksz));
_FDT(fdt_property_cell(fdt, "reg", cpu));
_FDT(fdt_property_string(fdt, "status", "okay"));
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
julien.thierry.kdev@gmail.com, maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH kvmtool 5/6] riscv: Add Zicbom extension support
Date: Tue, 18 Oct 2022 19:38:53 +0530 [thread overview]
Message-ID: <20221018140854.69846-6-apatel@ventanamicro.com> (raw)
In-Reply-To: <20221018140854.69846-1-apatel@ventanamicro.com>
From: Andrew Jones <ajones@ventanamicro.com>
When the Zicbom extension is available expose it to the guest.
Also provide the guest the size of the cache block through DT.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
riscv/fdt.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/riscv/fdt.c b/riscv/fdt.c
index 8d6da11..30d3460 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -19,6 +19,7 @@ struct isa_ext_info isa_info_arr[] = {
{"sstc", KVM_RISCV_ISA_EXT_SSTC},
{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
+ {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
};
static void dump_fdt(const char *dtb_file, void *fdt)
@@ -44,6 +45,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
int cpu, pos, i, index, valid_isa_len;
const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG";
int arr_sz = ARRAY_SIZE(isa_info_arr);
+ unsigned long cbom_blksz = 0;
_FDT(fdt_begin_node(fdt, "cpus"));
_FDT(fdt_property_cell(fdt, "#address-cells", 0x1));
@@ -78,6 +80,13 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
/* This extension is not available in hardware */
continue;
+ if (isa_info_arr[i].ext_id == KVM_RISCV_ISA_EXT_ZICBOM && !cbom_blksz) {
+ reg.id = RISCV_CONFIG_REG(zicbom_block_size);
+ reg.addr = (unsigned long)&cbom_blksz;
+ if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0)
+ die("KVM_GET_ONE_REG failed (config.zicbom_block_size)");
+ }
+
if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) {
pr_warning("Insufficient space to append ISA exension\n");
break;
@@ -97,6 +106,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm)
_FDT(fdt_property_string(fdt, "mmu-type",
"riscv,sv32"));
_FDT(fdt_property_string(fdt, "riscv,isa", cpu_isa));
+ if (cbom_blksz)
+ _FDT(fdt_property_cell(fdt, "riscv,cbom-block-size", cbom_blksz));
_FDT(fdt_property_cell(fdt, "reg", cpu));
_FDT(fdt_property_string(fdt, "status", "okay"));
--
2.34.1
next prev parent reply other threads:[~2022-10-18 14:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 14:08 [PATCH kvmtool 0/6] RISC-V Svinval, Zihintpause, anad Zicbom support Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-10-18 14:08 ` [PATCH kvmtool 1/6] Update UAPI headers based on Linux-6.1-rc1 Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-10-18 14:08 ` [PATCH kvmtool 2/6] riscv: Add Svinval extension support Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-10-18 14:08 ` [PATCH kvmtool 3/6] riscv: Add zihintpause " Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-10-18 14:08 ` [PATCH kvmtool 4/6] riscv: Move reg encoding helpers to kvm-cpu-arch.h Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-10-18 14:08 ` Anup Patel [this message]
2022-10-18 14:08 ` [PATCH kvmtool 5/6] riscv: Add Zicbom extension support Anup Patel
2022-10-18 14:08 ` [PATCH kvmtool 6/6] riscv: Add --disable-<xyz> options to allow user disable extensions Anup Patel
2022-10-18 14:08 ` Anup Patel
2022-11-07 12:20 ` [PATCH kvmtool 0/6] RISC-V Svinval, Zihintpause, anad Zicbom support Anup Patel
2022-11-07 12:20 ` Anup Patel
2022-11-08 15:33 ` Will Deacon
2022-11-08 15:33 ` Will Deacon
2022-11-08 17:38 ` Will Deacon
2022-11-08 17:38 ` Will Deacon
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