From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14EFEC38A2D for ; Tue, 25 Oct 2022 07:54:25 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E571E84E9E; Tue, 25 Oct 2022 09:53:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="tvFAfTjk"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D33BF848FB; Tue, 25 Oct 2022 09:52:34 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 31E45848FB for ; Tue, 25 Oct 2022 09:51:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Conor.Dooley@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666684287; x=1698220287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vt1+RXYL/ZVIhXJMPcsvxPzdIpu7qXsS8etkG8775tA=; b=tvFAfTjkNbJ+n1AcRP+VqPb5k+CJyyKsdgNuQfEtxhwhW6Dw9/nc/xnj cMGWm0d73KM9PLzFJvhinMLfHcTQuGlEeFa1lXgRjqSkRHDtKY/JFIPJK EHBI3DGydLkcyS1Cp1ViQg3PsROrBDDkG+xnO1KHHlekdc8C2giUWPvyO vybLdanKkTysEwxU6kmY00EQ80thoyBOroWxDGobc7dmMiuURePezCzQh Sm8S9XMltguO58Iq+xifHiftT1PyoGpwSGJ0yTIEe6xHVemw9K5lQzr7e 2xi12VUft7/cE1LYdzUeoyMMAQSTspGoLmxBKQOTrg01UsCTi4HO8mxCO A==; X-IronPort-AV: E=Sophos;i="5.95,211,1661842800"; d="scan'208";a="186266401" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Oct 2022 00:51:17 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 25 Oct 2022 00:51:17 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 25 Oct 2022 00:51:16 -0700 From: Conor Dooley To: Rick Chen , Leo , "Lukasz Majewski" , Sean Anderson CC: Conor Dooley , Padmarao Begari , Subject: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling Date: Tue, 25 Oct 2022 08:58:46 +0100 Message-ID: <20221025075848.110754-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221025075848.110754-1-conor.dooley@microchip.com> References: <20221025075848.110754-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The original devicetrees for PolarFire SoC messed up & defined the msspll's output as a fixed-frequency, 600 MHz clock & used that as the input for the clock controller node. The msspll is not a fixed frequency clock and later devicetrees handled this properly. Check the devicetree & if it is one of the fixed ones, register the msspll. Otherwise, skip registering it & pass the reference clock directly to the cfg clock registration function so that existing devicetrees are not broken by this change. As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for it, based on the one in Linux. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley --- drivers/clk/microchip/mpfs_clk.c | 23 ++++- drivers/clk/microchip/mpfs_clk.h | 8 ++ drivers/clk/microchip/mpfs_clk_msspll.c | 119 ++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index 7ba1218b56..f16f716f00 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -20,10 +20,12 @@ static int mpfs_clk_probe(struct udevice *dev) { struct clk *parent_clk = dev_get_priv(dev); struct clk clk_ahb = { .id = CLK_AHB }; + struct clk clk_msspll = { .id = CLK_MSSPLL }; void __iomem *base; + void __iomem *msspll_base; int ret; - base = dev_read_addr_ptr(dev); + base = dev_read_addr_index_ptr(dev, 0); if (!base) return -EINVAL; @@ -31,6 +33,25 @@ static int mpfs_clk_probe(struct udevice *dev) if (ret) return ret; + /* + * The original devicetrees for mpfs messed up & defined the msspll's + * output as a fixed-frequency, 600 MHz clock & used that as the input + * for the clock controller node. The msspll is however not a fixed + * frequency clock and later devicetrees handled this properly. Check + * the devicetree & if it is one of the fixed ones, register the msspll. + * Otherwise, skip registering it & pass the reference clock directly + * to the cfg clock registration function. + */ + msspll_base = dev_read_addr_index_ptr(dev, 1); + if (msspll_base) { + ret = mpfs_clk_register_msspll(msspll_base, parent_clk); + if (ret) + return ret; + + clk_request(dev, &clk_msspll); + parent_clk = &clk_msspll; + } + ret = mpfs_clk_register_cfgs(base, parent_clk); if (ret) return ret; diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h index 35cfeac92e..cb7d303e67 100644 --- a/drivers/clk/microchip/mpfs_clk.h +++ b/drivers/clk/microchip/mpfs_clk.h @@ -15,6 +15,14 @@ * Return: zero on success, or a negative error code. */ int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent); +/** + * mpfs_clk_register_msspll() - register the mss pll + * + * @base: base address of the mpfs system register. + * @parent: a pointer to parent clock. + * Return: zero on success, or a negative error code. + */ +int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent); /** * mpfs_clk_register_periphs() - register peripheral clocks * diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c new file mode 100644 index 0000000000..f37c0d8604 --- /dev/null +++ b/drivers/clk/microchip/mpfs_clk_msspll.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Microchip Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mpfs_clk.h" + +#define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock" + +/* address offset of control registers */ +#define REG_MSSPLL_REF_CR 0x08u +#define REG_MSSPLL_POSTDIV_CR 0x10u +#define REG_MSSPLL_SSCG_2_CR 0x2Cu + +#define MSSPLL_FBDIV_SHIFT 0x00u +#define MSSPLL_FBDIV_WIDTH 0x0Cu +#define MSSPLL_REFDIV_SHIFT 0x08u +#define MSSPLL_REFDIV_WIDTH 0x06u +#define MSSPLL_POSTDIV_SHIFT 0x08u +#define MSSPLL_POSTDIV_WIDTH 0x07u +#define MSSPLL_FIXED_DIV 4u + +/** + * struct mpfs_msspll_hw_clock + * @id: index of the msspll clock + * @name: the msspll clocks name + * @reg_offset: offset to the core complex's output of the msspll + * @shift: shift to the divider bit field of a msspll clock output + * @width: width of the divider bit field of the msspll clock output + * @flags: common clock framework flags + * @prate: the reference clock rate + * @hw: clock instance + */ +struct mpfs_msspll_hw_clock { + void __iomem *base; + unsigned int id; + const char *name; + u32 reg_offset; + u32 shift; + u32 width; + u32 flags; + u32 prate; + struct clk hw; +}; + +#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) + +static unsigned long mpfs_clk_msspll_recalc_rate(struct clk *hw) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + unsigned long temp; + + mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; + postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + + temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv); + return temp * mult; +} + +#define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \ + .id = _id, \ + .name = _name, \ + .shift = _shift, \ + .width = _width, \ + .reg_offset = _reg_offset, \ + .flags = _flags, \ +} + +static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { + CLK_PLL(CLK_MSSPLL, "clk_msspll", MSSPLL_FBDIV_SHIFT, + MSSPLL_FBDIV_WIDTH, REG_MSSPLL_SSCG_2_CR, 0), +}; + +int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent) +{ + int id, ret; + const char *name; + struct clk *hw; + + hw = &mpfs_msspll_clks[0].hw; + mpfs_msspll_clks[0].base = base; + mpfs_msspll_clks[0].prate = clk_get_rate(parent); + name = mpfs_msspll_clks[0].name; + ret = clk_register(hw, MPFS_MSSPLL_CLOCK, name, parent->dev->name); + if (ret) + ERR_PTR(ret); + id = mpfs_msspll_clks[0].id; + clk_dm(id, hw); + + return 0; +} + +const struct clk_ops mpfs_msspll_clk_ops = { + .get_rate = mpfs_clk_msspll_recalc_rate, +}; + +U_BOOT_DRIVER(mpfs_msspll_clock) = { + .name = MPFS_MSSPLL_CLOCK, + .id = UCLASS_CLK, + .ops = &mpfs_msspll_clk_ops, +}; + -- 2.38.0