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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id r15-20020ac8520f000000b003972790deb9sm3551881qtn.84.2022.10.31.05.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:52:35 -0700 (PDT) Date: Mon, 31 Oct 2022 13:52:32 +0100 From: Igor Mammedov To: Bernhard Beschow Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , qemu-trivial@nongnu.org, Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Ani Sinha Subject: Re: [PATCH v2 3/3] hw/i386/acpi-build: Resolve north rather than south bridges Message-ID: <20221031135232.118ae0ea@fedora> In-Reply-To: <20221028103419.93398-4-shentey@gmail.com> References: <20221028103419.93398-1-shentey@gmail.com> <20221028103419.93398-4-shentey@gmail.com> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.34; x86_64-redhat-linux-gnu) MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.048, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-trivial@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Oct 2022 12:52:42 -0000 On Fri, 28 Oct 2022 12:34:19 +0200 Bernhard Beschow wrote: > The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. Now that more > AML generation has been moved into the south bridges and since the > machines define themselves primarily through their north bridges, let's > switch to resolving the north bridges for AML generation instead. This > also allows for easier experimentation with different south bridges in > the "pc" machine, e.g. with PIIX4 and VT82xx. Patch looks fine to me in a sense that either would work. But the commit message lacks clear answer to 'why' and what issues it resolves or would resolve/make our easier life down to road. > Signed-off-by: Bernhard Beschow > --- > hw/i386/acpi-build.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 73d8a59737..d9eaa5fc4d 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -60,6 +60,7 @@ > #include "hw/i386/fw_cfg.h" > #include "hw/i386/ich9.h" > #include "hw/pci/pci_bus.h" > +#include "hw/pci-host/i440fx.h" > #include "hw/pci-host/q35.h" > #include "hw/i386/x86-iommu.h" > > @@ -1322,8 +1323,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > AcpiPmInfo *pm, AcpiMiscInfo *misc, > Range *pci_hole, Range *pci_hole64, MachineState *machine) > { > - Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); > - Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); > + Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); > + Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); > CrsRangeEntry *entry; > Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; > CrsRangeSet crs_range_set; > @@ -1344,13 +1345,13 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, > .oem_table_id = x86ms->oem_table_id }; > > - assert(!!piix != !!lpc); > + assert(!!i440fx != !!q35); > > acpi_table_begin(&table, table_data); > dsdt = init_aml_allocator(); > > build_dbg_aml(dsdt); > - if (piix) { > + if (i440fx) { > sb_scope = aml_scope("_SB"); > dev = aml_device("PCI0"); > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > @@ -1363,7 +1364,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); > } > build_piix4_pci0_int(dsdt); > - } else if (lpc) { > + } else if (q35) { > sb_scope = aml_scope("_SB"); > dev = aml_device("PCI0"); > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));