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Tsirkin" To: Lev Kujawski Cc: qemu-devel@nongnu.org, Eduardo Habkost , John Snow , qemu-block@nongnu.org, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Marcel Apfelbaum , Laurent Vivier , Yanan Wang , Paolo Bonzini , Thomas Huth , stefanha@redhat.com Subject: Re: [PATCH 1/2] qpci_device_enable: Allow for command bits hardwired to 0 Message-ID: <20221031163908-mutt-send-email-mst@kernel.org> References: <20221007095229-mutt-send-email-mst@kernel.org> <20221024094621.512806-1-lkujaw@mailbox.org> <20221024094621.512806-2-lkujaw@mailbox.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221024094621.512806-2-lkujaw@mailbox.org> Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.048, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Oct 24, 2022 at 09:46:20AM +0000, Lev Kujawski wrote: > Devices like the PIIX3/4 IDE controller do not support certain modes > of operation, such as memory space accesses, and indicate this lack of > support by hardwiring the applicable bits to zero. Extend the QEMU > PCI device testing framework to accommodate such devices. > > * tests/qtest/libqos/pci.h: Add the command_disabled word to indicate > bits hardwired to 0. > * tests/qtest/libqos/pci.c: Verify that hardwired bits are actually > hardwired. > > Signed-off-by: Lev Kujawski This patch makes the fuzzer unhappy with qpci_device_enable(): https://gitlab.com/qemu-project/qemu/-/jobs/3253817499 Will drop this patchset for now, pls address and resubmit. > --- > tests/qtest/libqos/pci.c | 13 +++++++------ > tests/qtest/libqos/pci.h | 1 + > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c > index b23d72346b..4f3d28d8d9 100644 > --- a/tests/qtest/libqos/pci.c > +++ b/tests/qtest/libqos/pci.c > @@ -220,18 +220,19 @@ int qpci_secondary_buses_init(QPCIBus *bus) > > void qpci_device_enable(QPCIDevice *dev) > { > - uint16_t cmd; > + const uint16_t enable_bits = > + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; > + uint16_t cmd, new_cmd; > > /* FIXME -- does this need to be a bus callout? */ > cmd = qpci_config_readw(dev, PCI_COMMAND); > - cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; > + cmd |= enable_bits; > qpci_config_writew(dev, PCI_COMMAND, cmd); > > /* Verify the bits are now set. */ > - cmd = qpci_config_readw(dev, PCI_COMMAND); > - g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO); > - g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY); > - g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER); > + new_cmd = qpci_config_readw(dev, PCI_COMMAND); > + new_cmd &= enable_bits; > + g_assert_cmphex(new_cmd, ==, enable_bits & ~dev->command_disabled); > } > > /** > diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h > index 8389614523..eaedb98588 100644 > --- a/tests/qtest/libqos/pci.h > +++ b/tests/qtest/libqos/pci.h > @@ -68,6 +68,7 @@ struct QPCIDevice > bool msix_enabled; > QPCIBar msix_table_bar, msix_pba_bar; > uint64_t msix_table_off, msix_pba_off; > + uint16_t command_disabled; > }; > > struct QPCIAddress { > -- > 2.34.1