From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC5BDC433FE for ; Mon, 7 Nov 2022 07:29:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IoGm/YvIu7CmIfCQIQ4ugMZNbm3cqB9AGKlSebBMzug=; b=ClslaDNwjaAESKKLT95bmCrd9D lSDElYpFZBnje9+ObPxMrFtC+U444l/zFQeKNtVs10A4kUpsaz+UNQYGnBM/CBJceXLUSH4GMQ7lj ZyOeSQUiJ/js3z5sJYBOnBI1Pql7k7OokCFDcA9FXUMh4cjshzoHMp+1CPniA4TPz1gYRAZUhL6qw VRj6QURfUP3/QK8sHl7oi/VzczANgSdrja75JzSNizi+K4bs7BpmSzJrvpxUI/QBzarCNpV4XvX3O 6yID2v+zc7K9K3VPwlDInEmpx51QGeu3P7PEILO6JYzHaySVqPPdezw+grTpP/wwGqjqhZ3J7TGIf GpVNp7zw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwZ2-00CNi8-IA; Mon, 07 Nov 2022 07:29:00 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwTh-00CKKM-2A; Mon, 07 Nov 2022 07:23:32 +0000 X-UUID: b1f61eaf3b954a75b6e570417908f996-20221107 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IoGm/YvIu7CmIfCQIQ4ugMZNbm3cqB9AGKlSebBMzug=; b=AvlPnGPsLVquIzfZ/au1BCZFPAD3Tva/Dc7eqL9yAcyLPFsn3o7lhZeePGpg2vUyE2SWRjvGY2AlbHzfw9cnsp2cRIZwIShpvtIBJwHoS4l+nAtA3f6/lSh0fobDXgWETKM0Y0QW2xF3ODr6mQGPAyssacacylDsxDK7nkvshtY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:ba7e45b6-5377-4f9c-a834-fe880395f3dc,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:62cd327,CLOUDID:fe9ecb90-1a78-4832-bd08-74b1519dcfbf,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b1f61eaf3b954a75b6e570417908f996-20221107 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 671363663; Mon, 07 Nov 2022 00:23:23 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 7 Nov 2022 15:22:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 7 Nov 2022 15:22:47 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Subject: [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Date: Mon, 7 Nov 2022 15:22:40 +0800 Message-ID: <20221107072243.15748-9-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221107072243.15748-1-nancy.lin@mediatek.com> References: <20221107072243.15748-1-nancy.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_232329_181210_8B65181E X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add mmsys for support 64 reset bits. It is a preparation for MT8195 vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. 1. Add the number of reset bits in mmsys private data 2. move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Bo-Chen Chen Reviewed-by: Nícolas F. R. A. Prado --- drivers/soc/mediatek/mtk-mmsys.c | 40 +++++++++++++++++++++----------- drivers/soc/mediatek/mtk-mmsys.h | 1 + 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1bd2f8e45d85..78601372512f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -20,6 +20,8 @@ #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -51,6 +53,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -58,6 +61,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { @@ -65,6 +69,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .routes = mmsys_mt8186_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -72,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { @@ -206,13 +212,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; + u32 reg; + + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + reg = mmsys->data->sw0_rst_offset + offset; spin_lock_irqsave(&mmsys->lock, flags); if (assert) - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); else - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -267,20 +279,22 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - spin_lock_init(&mmsys->lock); + mmsys->data = of_device_get_match_data(&pdev->dev); - mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; - mmsys->rcdev.of_node = pdev->dev.of_node; - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); - if (ret) { - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); - return ret; + if (mmsys->data->num_resets > 0) { + spin_lock_init(&mmsys->lock); + + mmsys->rcdev.owner = THIS_MODULE; + mmsys->rcdev.nr_resets = mmsys->data->num_resets; + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; + mmsys->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); + if (ret) { + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); + return ret; + } } - mmsys->data = of_device_get_match_data(&pdev->dev); - #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 77f37f8c715b..e19994749adb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -91,6 +91,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u32 num_resets; }; /* -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A744EC4332F for ; Mon, 7 Nov 2022 07:29:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OrsenNlxu2Q2oYJSNAFUjFOaj0WZUoPvcpzgh+9k9O0=; b=unOdeHktnUxQ0k g62QMb9TpxoQVfgzIjaWEBM83UMWic0Z0a3NojdL/ZulNZ4OyuduemYjrsnCY99i5o62QN8awYL5D LigoAc96Zyk/z59+lQovg044dhffJSTCmt/yfhEWcUorbz8sjUwaojJkBw/IPMZDpEXbqovxWTjvw /vT9jU+CoQn4XjbR5D/XCfZaMnEbiRPpP5tSnr+H5W3CfwqiTKRrLuZ1UogdCMmM2PrsCBF2oeDSd xAacsXD1kSYYNKhrFW6fhVWcuAQy4JfuqL9r9ld5A7fe1OMgIbUv9/Pi+tMbA3mXe5PhNhfFlUQU1 BbIHo4dm2ikybPgIz2lA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwYT-00CNPW-A5; Mon, 07 Nov 2022 07:28:25 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1orwTh-00CKKM-2A; Mon, 07 Nov 2022 07:23:32 +0000 X-UUID: b1f61eaf3b954a75b6e570417908f996-20221107 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IoGm/YvIu7CmIfCQIQ4ugMZNbm3cqB9AGKlSebBMzug=; b=AvlPnGPsLVquIzfZ/au1BCZFPAD3Tva/Dc7eqL9yAcyLPFsn3o7lhZeePGpg2vUyE2SWRjvGY2AlbHzfw9cnsp2cRIZwIShpvtIBJwHoS4l+nAtA3f6/lSh0fobDXgWETKM0Y0QW2xF3ODr6mQGPAyssacacylDsxDK7nkvshtY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:ba7e45b6-5377-4f9c-a834-fe880395f3dc,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:62cd327,CLOUDID:fe9ecb90-1a78-4832-bd08-74b1519dcfbf,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b1f61eaf3b954a75b6e570417908f996-20221107 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 671363663; Mon, 07 Nov 2022 00:23:23 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 7 Nov 2022 15:22:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 7 Nov 2022 15:22:47 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Subject: [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Date: Mon, 7 Nov 2022 15:22:40 +0800 Message-ID: <20221107072243.15748-9-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221107072243.15748-1-nancy.lin@mediatek.com> References: <20221107072243.15748-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_232329_181210_8B65181E X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org QWRkIG1tc3lzIGZvciBzdXBwb3J0IDY0IHJlc2V0IGJpdHMuIEl0IGlzIGEgcHJlcGFyYXRpb24g Zm9yIE1UODE5NQp2ZG9zeXMxIEhXIHJlc2V0LiBNVDgxOTUgdmRvc3lzMSBoYXMgbW9yZSB0aGFu IDMyIHJlc2V0IGJpdHMuCgoxLiBBZGQgdGhlIG51bWJlciBvZiByZXNldCBiaXRzIGluIG1tc3lz IHByaXZhdGUgZGF0YQoyLiBtb3ZlIHRoZSB3aG9sZSAicmVzZXQgcmVnaXN0ZXIgY29kZSBzZWN0 aW9uIiBiZWhpbmQgdGhlCiJnZXQgbW1zeXMtPmRhdGEiIGNvZGUgc2VjdGlvbiBmb3IgZ2V0dGlu ZyB0aGUgbnVtX3Jlc2V0cyBpbiBtbXN5cy0+ZGF0YS4KClNpZ25lZC1vZmYtYnk6IE5hbmN5Lkxp biA8bmFuY3kubGluQG1lZGlhdGVrLmNvbT4KUmV2aWV3ZWQtYnk6IEFuZ2Vsb0dpb2FjY2hpbm8g RGVsIFJlZ25vIDxhbmdlbG9naW9hY2NoaW5vLmRlbHJlZ25vQGNvbGxhYm9yYS5jb20+ClJldmll d2VkLWJ5OiBDSyBIdSA8Y2suaHVAbWVkaWF0ZWsuY29tPgpUZXN0ZWQtYnk6IEJvLUNoZW4gQ2hl biA8cmV4LWJjLmNoZW5AbWVkaWF0ZWsuY29tPgpSZXZpZXdlZC1ieTogTsOtY29sYXMgRi4gUi4g QS4gUHJhZG8gPG5mcmFwcmFkb0Bjb2xsYWJvcmEuY29tPgotLS0KIGRyaXZlcnMvc29jL21lZGlh dGVrL210ay1tbXN5cy5jIHwgNDAgKysrKysrKysrKysrKysrKysrKysrLS0tLS0tLS0tLS0KIGRy aXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5oIHwgIDEgKwogMiBmaWxlcyBjaGFuZ2VkLCAy OCBpbnNlcnRpb25zKCspLCAxMyBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL3Nv Yy9tZWRpYXRlay9tdGstbW1zeXMuYyBiL2RyaXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5j CmluZGV4IDFiZDJmOGU0NWQ4NS4uNzg2MDEzNzI1MTJmIDEwMDY0NAotLS0gYS9kcml2ZXJzL3Nv Yy9tZWRpYXRlay9tdGstbW1zeXMuYworKysgYi9kcml2ZXJzL3NvYy9tZWRpYXRlay9tdGstbW1z eXMuYwpAQCAtMjAsNiArMjAsOCBAQAogI2luY2x1ZGUgIm10ODE5NS1tbXN5cy5oIgogI2luY2x1 ZGUgIm10ODM2NS1tbXN5cy5oIgogCisjZGVmaW5lIE1NU1lTX1NXX1JFU0VUX1BFUl9SRUcgMzIK Kwogc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfbW1zeXNfZHJpdmVyX2RhdGEgbXQyNzAxX21tc3lz X2RyaXZlcl9kYXRhID0gewogCS5jbGtfZHJpdmVyID0gImNsay1tdDI3MDEtbW0iLAogCS5yb3V0 ZXMgPSBtbXN5c19kZWZhdWx0X3JvdXRpbmdfdGFibGUsCkBAIC01MSw2ICs1Myw3IEBAIHN0YXRp YyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9kYXRhIG10ODE3M19tbXN5c19kcml2ZXJf ZGF0YSA9IHsKIAkucm91dGVzID0gbW1zeXNfZGVmYXVsdF9yb3V0aW5nX3RhYmxlLAogCS5udW1f cm91dGVzID0gQVJSQVlfU0laRShtbXN5c19kZWZhdWx0X3JvdXRpbmdfdGFibGUpLAogCS5zdzBf cnN0X29mZnNldCA9IE1UODE4M19NTVNZU19TVzBfUlNUX0IsCisJLm51bV9yZXNldHMgPSAzMiwK IH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9kYXRhIG10ODE4M19t bXN5c19kcml2ZXJfZGF0YSA9IHsKQEAgLTU4LDYgKzYxLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVj dCBtdGtfbW1zeXNfZHJpdmVyX2RhdGEgbXQ4MTgzX21tc3lzX2RyaXZlcl9kYXRhID0gewogCS5y b3V0ZXMgPSBtbXN5c19tdDgxODNfcm91dGluZ190YWJsZSwKIAkubnVtX3JvdXRlcyA9IEFSUkFZ X1NJWkUobW1zeXNfbXQ4MTgzX3JvdXRpbmdfdGFibGUpLAogCS5zdzBfcnN0X29mZnNldCA9IE1U ODE4M19NTVNZU19TVzBfUlNUX0IsCisJLm51bV9yZXNldHMgPSAzMiwKIH07CiAKIHN0YXRpYyBj b25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9kYXRhIG10ODE4Nl9tbXN5c19kcml2ZXJfZGF0 YSA9IHsKQEAgLTY1LDYgKzY5LDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfbW1zeXNfZHJp dmVyX2RhdGEgbXQ4MTg2X21tc3lzX2RyaXZlcl9kYXRhID0gewogCS5yb3V0ZXMgPSBtbXN5c19t dDgxODZfcm91dGluZ190YWJsZSwKIAkubnVtX3JvdXRlcyA9IEFSUkFZX1NJWkUobW1zeXNfbXQ4 MTg2X3JvdXRpbmdfdGFibGUpLAogCS5zdzBfcnN0X29mZnNldCA9IE1UODE4Nl9NTVNZU19TVzBf UlNUX0IsCisJLm51bV9yZXNldHMgPSAzMiwKIH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRr X21tc3lzX2RyaXZlcl9kYXRhIG10ODE5Ml9tbXN5c19kcml2ZXJfZGF0YSA9IHsKQEAgLTcyLDYg Kzc3LDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBtdGtfbW1zeXNfZHJpdmVyX2RhdGEgbXQ4MTky X21tc3lzX2RyaXZlcl9kYXRhID0gewogCS5yb3V0ZXMgPSBtbXN5c19tdDgxOTJfcm91dGluZ190 YWJsZSwKIAkubnVtX3JvdXRlcyA9IEFSUkFZX1NJWkUobW1zeXNfbXQ4MTkyX3JvdXRpbmdfdGFi bGUpLAogCS5zdzBfcnN0X29mZnNldCA9IE1UODE4Nl9NTVNZU19TVzBfUlNUX0IsCisJLm51bV9y ZXNldHMgPSAzMiwKIH07CiAKIHN0YXRpYyBjb25zdCBzdHJ1Y3QgbXRrX21tc3lzX2RyaXZlcl9k YXRhIG10ODE5NV92ZG9zeXMwX2RyaXZlcl9kYXRhID0gewpAQCAtMjA2LDEzICsyMTIsMTkgQEAg c3RhdGljIGludCBtdGtfbW1zeXNfcmVzZXRfdXBkYXRlKHN0cnVjdCByZXNldF9jb250cm9sbGVy X2RldiAqcmNkZXYsIHVuc2lnbmVkIGwKIHsKIAlzdHJ1Y3QgbXRrX21tc3lzICptbXN5cyA9IGNv bnRhaW5lcl9vZihyY2Rldiwgc3RydWN0IG10a19tbXN5cywgcmNkZXYpOwogCXVuc2lnbmVkIGxv bmcgZmxhZ3M7CisJdTMyIG9mZnNldDsKKwl1MzIgcmVnOworCisJb2Zmc2V0ID0gKGlkIC8gTU1T WVNfU1dfUkVTRVRfUEVSX1JFRykgKiBzaXplb2YodTMyKTsKKwlpZCA9IGlkICUgTU1TWVNfU1df UkVTRVRfUEVSX1JFRzsKKwlyZWcgPSBtbXN5cy0+ZGF0YS0+c3cwX3JzdF9vZmZzZXQgKyBvZmZz ZXQ7CiAKIAlzcGluX2xvY2tfaXJxc2F2ZSgmbW1zeXMtPmxvY2ssIGZsYWdzKTsKIAogCWlmIChh c3NlcnQpCi0JCW10a19tbXN5c191cGRhdGVfYml0cyhtbXN5cywgbW1zeXMtPmRhdGEtPnN3MF9y c3Rfb2Zmc2V0LCBCSVQoaWQpLCAwLCBOVUxMKTsKKwkJbXRrX21tc3lzX3VwZGF0ZV9iaXRzKG1t c3lzLCByZWcsIEJJVChpZCksIDAsIE5VTEwpOwogCWVsc2UKLQkJbXRrX21tc3lzX3VwZGF0ZV9i aXRzKG1tc3lzLCBtbXN5cy0+ZGF0YS0+c3cwX3JzdF9vZmZzZXQsIEJJVChpZCksIEJJVChpZCks IE5VTEwpOworCQltdGtfbW1zeXNfdXBkYXRlX2JpdHMobW1zeXMsIHJlZywgQklUKGlkKSwgQklU KGlkKSwgTlVMTCk7CiAKIAlzcGluX3VubG9ja19pcnFyZXN0b3JlKCZtbXN5cy0+bG9jaywgZmxh Z3MpOwogCkBAIC0yNjcsMjAgKzI3OSwyMiBAQCBzdGF0aWMgaW50IG10a19tbXN5c19wcm9iZShz dHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQogCQlyZXR1cm4gcmV0OwogCX0KIAotCXNwaW5f bG9ja19pbml0KCZtbXN5cy0+bG9jayk7CisJbW1zeXMtPmRhdGEgPSBvZl9kZXZpY2VfZ2V0X21h dGNoX2RhdGEoJnBkZXYtPmRldik7CiAKLQltbXN5cy0+cmNkZXYub3duZXIgPSBUSElTX01PRFVM RTsKLQltbXN5cy0+cmNkZXYubnJfcmVzZXRzID0gMzI7Ci0JbW1zeXMtPnJjZGV2Lm9wcyA9ICZt dGtfbW1zeXNfcmVzZXRfb3BzOwotCW1tc3lzLT5yY2Rldi5vZl9ub2RlID0gcGRldi0+ZGV2Lm9m X25vZGU7Ci0JcmV0ID0gZGV2bV9yZXNldF9jb250cm9sbGVyX3JlZ2lzdGVyKCZwZGV2LT5kZXYs ICZtbXN5cy0+cmNkZXYpOwotCWlmIChyZXQpIHsKLQkJZGV2X2VycigmcGRldi0+ZGV2LCAiQ291 bGRuJ3QgcmVnaXN0ZXIgbW1zeXMgcmVzZXQgY29udHJvbGxlcjogJWRcbiIsIHJldCk7Ci0JCXJl dHVybiByZXQ7CisJaWYgKG1tc3lzLT5kYXRhLT5udW1fcmVzZXRzID4gMCkgeworCQlzcGluX2xv Y2tfaW5pdCgmbW1zeXMtPmxvY2spOworCisJCW1tc3lzLT5yY2Rldi5vd25lciA9IFRISVNfTU9E VUxFOworCQltbXN5cy0+cmNkZXYubnJfcmVzZXRzID0gbW1zeXMtPmRhdGEtPm51bV9yZXNldHM7 CisJCW1tc3lzLT5yY2Rldi5vcHMgPSAmbXRrX21tc3lzX3Jlc2V0X29wczsKKwkJbW1zeXMtPnJj ZGV2Lm9mX25vZGUgPSBwZGV2LT5kZXYub2Zfbm9kZTsKKwkJcmV0ID0gZGV2bV9yZXNldF9jb250 cm9sbGVyX3JlZ2lzdGVyKCZwZGV2LT5kZXYsICZtbXN5cy0+cmNkZXYpOworCQlpZiAocmV0KSB7 CisJCQlkZXZfZXJyKCZwZGV2LT5kZXYsICJDb3VsZG4ndCByZWdpc3RlciBtbXN5cyByZXNldCBj b250cm9sbGVyOiAlZFxuIiwgcmV0KTsKKwkJCXJldHVybiByZXQ7CisJCX0KIAl9CiAKLQltbXN5 cy0+ZGF0YSA9IG9mX2RldmljZV9nZXRfbWF0Y2hfZGF0YSgmcGRldi0+ZGV2KTsKLQogI2lmIElT X1JFQUNIQUJMRShDT05GSUdfTVRLX0NNRFEpCiAJcmV0ID0gY21kcV9kZXZfZ2V0X2NsaWVudF9y ZWcoZGV2LCAmbW1zeXMtPmNtZHFfYmFzZSwgMCk7CiAJaWYgKHJldCkKZGlmZiAtLWdpdCBhL2Ry aXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5oIGIvZHJpdmVycy9zb2MvbWVkaWF0ZWsvbXRr LW1tc3lzLmgKaW5kZXggNzdmMzdmOGM3MTViLi5lMTk5OTQ3NDlhZGIgMTAwNjQ0Ci0tLSBhL2Ry aXZlcnMvc29jL21lZGlhdGVrL210ay1tbXN5cy5oCisrKyBiL2RyaXZlcnMvc29jL21lZGlhdGVr L210ay1tbXN5cy5oCkBAIC05MSw2ICs5MSw3IEBAIHN0cnVjdCBtdGtfbW1zeXNfZHJpdmVyX2Rh dGEgewogCWNvbnN0IHN0cnVjdCBtdGtfbW1zeXNfcm91dGVzICpyb3V0ZXM7CiAJY29uc3QgdW5z aWduZWQgaW50IG51bV9yb3V0ZXM7CiAJY29uc3QgdTE2IHN3MF9yc3Rfb2Zmc2V0OworCWNvbnN0 IHUzMiBudW1fcmVzZXRzOwogfTsKIAogLyoKLS0gCjIuMTguMAoKCl9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBs aXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5m cmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E20AC433FE for ; Mon, 7 Nov 2022 07:23:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39E0910E213; Mon, 7 Nov 2022 07:23:07 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id E78AA10E200 for ; Mon, 7 Nov 2022 07:22:52 +0000 (UTC) X-UUID: 40a2f2bc01044810b568927bdd681e8e-20221107 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IoGm/YvIu7CmIfCQIQ4ugMZNbm3cqB9AGKlSebBMzug=; b=AvlPnGPsLVquIzfZ/au1BCZFPAD3Tva/Dc7eqL9yAcyLPFsn3o7lhZeePGpg2vUyE2SWRjvGY2AlbHzfw9cnsp2cRIZwIShpvtIBJwHoS4l+nAtA3f6/lSh0fobDXgWETKM0Y0QW2xF3ODr6mQGPAyssacacylDsxDK7nkvshtY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12, REQID:29560fc5-4edb-48d4-9443-bb9d6c249740, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:62cd327, CLOUDID:8869a4eb-84ac-4628-a416-bc50d5503da6, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 40a2f2bc01044810b568927bdd681e8e-20221107 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1210314631; Mon, 07 Nov 2022 15:22:48 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 7 Nov 2022 15:22:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 7 Nov 2022 15:22:47 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , , Subject: [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Date: Mon, 7 Nov 2022 15:22:40 +0800 Message-ID: <20221107072243.15748-9-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221107072243.15748-1-nancy.lin@mediatek.com> References: <20221107072243.15748-1-nancy.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Yongqiang Niu , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nathan Chancellor , "Nancy . Lin" , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add mmsys for support 64 reset bits. It is a preparation for MT8195 vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. 1. Add the number of reset bits in mmsys private data 2. move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Bo-Chen Chen Reviewed-by: Nícolas F. R. A. Prado --- drivers/soc/mediatek/mtk-mmsys.c | 40 +++++++++++++++++++++----------- drivers/soc/mediatek/mtk-mmsys.h | 1 + 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1bd2f8e45d85..78601372512f 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -20,6 +20,8 @@ #include "mt8195-mmsys.h" #include "mt8365-mmsys.h" +#define MMSYS_SW_RESET_PER_REG 32 + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", .routes = mmsys_default_routing_table, @@ -51,6 +53,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -58,6 +61,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { @@ -65,6 +69,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { .routes = mmsys_mt8186_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -72,6 +77,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, + .num_resets = 32, }; static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { @@ -206,13 +212,19 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l { struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); unsigned long flags; + u32 offset; + u32 reg; + + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); + id = id % MMSYS_SW_RESET_PER_REG; + reg = mmsys->data->sw0_rst_offset + offset; spin_lock_irqsave(&mmsys->lock, flags); if (assert) - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), 0, NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), 0, NULL); else - mtk_mmsys_update_bits(mmsys, mmsys->data->sw0_rst_offset, BIT(id), BIT(id), NULL); + mtk_mmsys_update_bits(mmsys, reg, BIT(id), BIT(id), NULL); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -267,20 +279,22 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } - spin_lock_init(&mmsys->lock); + mmsys->data = of_device_get_match_data(&pdev->dev); - mmsys->rcdev.owner = THIS_MODULE; - mmsys->rcdev.nr_resets = 32; - mmsys->rcdev.ops = &mtk_mmsys_reset_ops; - mmsys->rcdev.of_node = pdev->dev.of_node; - ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); - if (ret) { - dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); - return ret; + if (mmsys->data->num_resets > 0) { + spin_lock_init(&mmsys->lock); + + mmsys->rcdev.owner = THIS_MODULE; + mmsys->rcdev.nr_resets = mmsys->data->num_resets; + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; + mmsys->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); + if (ret) { + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); + return ret; + } } - mmsys->data = of_device_get_match_data(&pdev->dev); - #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 77f37f8c715b..e19994749adb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -91,6 +91,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u32 num_resets; }; /* -- 2.18.0