From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6F761841 for ; Tue, 15 Nov 2022 00:29:41 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 15620ED1; Mon, 14 Nov 2022 16:29:41 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 820973F663; Mon, 14 Nov 2022 16:29:32 -0800 (PST) Date: Tue, 15 Nov 2022 00:28:08 +0000 From: Andre Przywara To: Jernej =?UTF-8?B?xaBrcmFiZWM=?= Cc: Chen-Yu Tsai , Samuel Holland , Rob Herring , Krzysztof Kozlowski , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals Message-ID: <20221115002808.5456008b@slackpad.lan> In-Reply-To: <1920557.yKVeVyVuyW@kista> References: <20221107005433.11079-1-andre.przywara@arm.com> <1920557.yKVeVyVuyW@kista> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Mon, 07 Nov 2022 20:33:47 +0100 Jernej =C5=A0krabec wrote: Hi Jernej, thanks for the reviews! > Dne ponedeljek, 07. november 2022 ob 01:54:23 CET je Andre Przywara=20 > napisal(a): > > This is a fixed version of the initial post. I dropped the two patches > > that were already applied by the respective maintainers, and fixed the > > smaller issues mentioned in the review. > > This adds v2 of the series enabling the "Lctech Pi F1C200s" board on to= p, > > also with the comments addressed. =20 >=20 > Please don't combine series if not agreed upon before. Now whole series w= ill=20 > be delayed until USB is sorted out. Apologies for that. Indeed I should have added the board DT to the USB series instead, as there is no dependency to anything in here. If you don't mind, I will send a v3 with the last three patches dropped, and the ACKs and R-b's added (and that one line in the commit message fixed). Cheers, Andre >=20 > Best regards, > Jernej >=20 > > The whole series goes on top of v3 of Icenowy's F1C100s USB support > > series [1]. There is no real conflict, but the lctech-pi.dts file > > references the new USB DT nodes from the .dtsi. > >=20 > > I put a git repo with all those patches up here: > > https://github.com/apritzel/linux/commits/f1c100s-devices-v2 > >=20 > > For a changelog see below. > >=20 > > [1] > > https://lore.kernel.org/linux-arm-kernel/20221106154826.6687-1-andre.pr= zywa > > ra@arm.com/T/#t > >=20 > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > The Allwinner F1C100s series of SoCs shares many peripherals with other > > Allwinner SoCs. Since they are compatible, we can use the existing > > drivers, and just need to enable the devices in the DT. > >=20 > > This series adds the I2C controllers, the PWM device, the CIR (infrared) > > device and the LRADC (aka. KEYADC, low res ADC) to the F1C100s .dtsi, so > > boards can just use them by setting 'status =3D "okay";'. > >=20 > > The only thing missing driver-wise is the IR mod clock, which was not > > modeled in our CCU driver. Patch 4/10 fixes that. > >=20 > > For every device there is one patch that adds the new compatible string > > to the DT binding, and another patch to add the DT node. > >=20 > > This has been tested on the Lctech Pi F1C200s board, by: > > - Connecting an LED to PE6, and configuring this as the PWM pin in the = DT. > > Doing a sweep on /sys/class/pwm/pwm1/duty_cycle made the LED fade out. > > - Configuring PD0/PD12 as I2C0, and letting i2c-detect find the on-board > > NS2009 I2C chip. > > - Connecting two resistors to the "ADC" pin, and configuring them as two > > buttons in the DT. /dev/input/event0 properly reported button presses. > > - Connecting an infrared receiver to PE11, configured as CIR. > > ir-keytable reported key presses on a remote control. > >=20 > > All those (basic) tests were successful, and prove that the peripherals > > do work and are compatible. > >=20 > > The final three patches add the binding docs and the .dts file for the > > Lctech Pi F1C200s development board. > >=20 > > Please have a look and test on your hardware, if possible. > >=20 > > Cheers, > > Andre > >=20 > > Changelog v1 ... v2: > > - dropped former patch 3/9 and 8/9: already applied > > - increase register frame size in DT for PWM and LRADC > > - drop I2C1 pins from pinctroller DT node > > - increase IR mod clock mux to 2 bits > > - fix mistyped comma in vendor prefix name > > - drop unneeded mmc0 and spi0 aliases from Lctech Pi DT > > - add /omit-if-no-ref/ tag to UART1 pins > > - add ACKs and Reviewed-by tags > >=20 > >=20 > > Andre Przywara (10): > > dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible > > ARM: dts: suniv: f1c100s: add PWM node > > ARM: dts: suniv: f1c100s: add I2C DT nodes > > clk: sunxi-ng: f1c100s: Add IR mod clock > > dt-bindings: media: IR: Add F1C100s IR compatible string > > ARM: dts: suniv: f1c100s: add CIR DT node > > ARM: dts: suniv: f1c100s: add LRADC node > > dt-bindings: vendor-prefixes: add Lctech name > > dt-bindings: arm: sunxi: add compatible strings for Lctech Pi > > ARM: dts: suniv: Add Lctech Pi F1C200s devicetree > >=20 > > .../devicetree/bindings/arm/sunxi.yaml | 6 ++ > > .../media/allwinner,sun4i-a10-ir.yaml | 1 + > > .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 4 +- > > .../devicetree/bindings/vendor-prefixes.yaml | 2 + > > arch/arm/boot/dts/Makefile | 1 + > > arch/arm/boot/dts/suniv-f1c100s.dtsi | 76 ++++++++++++++++++ > > arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 78 +++++++++++++++++++ > > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 11 ++- > > drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 2 +- > > include/dt-bindings/clock/suniv-ccu-f1c100s.h | 2 + > > 10 files changed, 180 insertions(+), 3 deletions(-) > > create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts > >=20 > > -- > > 2.35.5 =20 >=20 >=20 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CCBCC433FE for ; Tue, 15 Nov 2022 00:31:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uc+7IxREXxsr8SqfXOSsSQdHe6e1en9U2hc919HZL6g=; b=g/3M/P7m05XdPh 65BjA4ayjdAq+o7mxVfDrb4jYOlcVoVbkFJDH3bDEnVbmrSi3yV8XprCQeleggJKwx61lxNEKzlPK nY1czLWoQiQo7YwkkMlUUmB5v0xL0eA5QtH6qIX601FIuKJ7JdjyxpT5Mkoq3G/W5ijGx88XjIeR2 i8CajTmnigoX9C6O8t5tVtJYIQanvpmgMjTc5QKz9VnyK9xwEdRw4OISGYccuAbHLkVrZI/ll8Ntt N2ZSUcR1n2c4RaVgsoVA10knK9umTe7+Am74P0y7oG5st/JH5+ey/52f0lNnjVkYCFtWeT8t4LzWZ 7KlnVOlz2ApPL/vae9pg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oujph-0067qV-In; Tue, 15 Nov 2022 00:29:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oujpd-0067ly-Dy for linux-arm-kernel@lists.infradead.org; Tue, 15 Nov 2022 00:29:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 15620ED1; Mon, 14 Nov 2022 16:29:41 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 820973F663; Mon, 14 Nov 2022 16:29:32 -0800 (PST) Date: Tue, 15 Nov 2022 00:28:08 +0000 From: Andre Przywara To: Jernej =?UTF-8?B?xaBrcmFiZWM=?= Cc: Chen-Yu Tsai , Samuel Holland , Rob Herring , Krzysztof Kozlowski , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: Re: [PATCH v2 00/10] ARM: dts: suniv: F1C100s: add more peripherals Message-ID: <20221115002808.5456008b@slackpad.lan> In-Reply-To: <1920557.yKVeVyVuyW@kista> References: <20221107005433.11079-1-andre.przywara@arm.com> <1920557.yKVeVyVuyW@kista> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221114_162941_587450_DA8107D6 X-CRM114-Status: GOOD ( 39.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCAwNyBOb3YgMjAyMiAyMDozMzo0NyArMDEwMApKZXJuZWogxaBrcmFiZWMgPGplcm5l ai5za3JhYmVjQGdtYWlsLmNvbT4gd3JvdGU6CgpIaSBKZXJuZWosCgp0aGFua3MgZm9yIHRoZSBy ZXZpZXdzIQoKPiBEbmUgcG9uZWRlbGplaywgMDcuIG5vdmVtYmVyIDIwMjIgb2IgMDE6NTQ6MjMg Q0VUIGplIEFuZHJlIFByenl3YXJhIAo+IG5hcGlzYWwoYSk6Cj4gPiBUaGlzIGlzIGEgZml4ZWQg dmVyc2lvbiBvZiB0aGUgaW5pdGlhbCBwb3N0LiBJIGRyb3BwZWQgdGhlIHR3byBwYXRjaGVzCj4g PiB0aGF0IHdlcmUgYWxyZWFkeSBhcHBsaWVkIGJ5IHRoZSByZXNwZWN0aXZlIG1haW50YWluZXJz LCBhbmQgZml4ZWQgdGhlCj4gPiBzbWFsbGVyIGlzc3VlcyBtZW50aW9uZWQgaW4gdGhlIHJldmll dy4KPiA+IFRoaXMgYWRkcyB2MiBvZiB0aGUgc2VyaWVzIGVuYWJsaW5nIHRoZSAiTGN0ZWNoIFBp IEYxQzIwMHMiIGJvYXJkIG9uIHRvcCwKPiA+IGFsc28gd2l0aCB0aGUgY29tbWVudHMgYWRkcmVz c2VkLiAgCj4gCj4gUGxlYXNlIGRvbid0IGNvbWJpbmUgc2VyaWVzIGlmIG5vdCBhZ3JlZWQgdXBv biBiZWZvcmUuIE5vdyB3aG9sZSBzZXJpZXMgd2lsbCAKPiBiZSBkZWxheWVkIHVudGlsIFVTQiBp cyBzb3J0ZWQgb3V0LgoKQXBvbG9naWVzIGZvciB0aGF0LiBJbmRlZWQgSSBzaG91bGQgaGF2ZSBh ZGRlZCB0aGUgYm9hcmQgRFQgdG8gdGhlIFVTQgpzZXJpZXMgaW5zdGVhZCwgYXMgdGhlcmUgaXMg bm8gZGVwZW5kZW5jeSB0byBhbnl0aGluZyBpbiBoZXJlLgoKSWYgeW91IGRvbid0IG1pbmQsIEkg d2lsbCBzZW5kIGEgdjMgd2l0aCB0aGUgbGFzdCB0aHJlZSBwYXRjaGVzCmRyb3BwZWQsIGFuZCB0 aGUgQUNLcyBhbmQgUi1iJ3MgYWRkZWQgKGFuZCB0aGF0IG9uZSBsaW5lIGluIHRoZSBjb21taXQK bWVzc2FnZSBmaXhlZCkuCgpDaGVlcnMsCkFuZHJlCgo+IAo+IEJlc3QgcmVnYXJkcywKPiBKZXJu ZWoKPiAKPiA+IFRoZSB3aG9sZSBzZXJpZXMgZ29lcyBvbiB0b3Agb2YgdjMgb2YgSWNlbm93eSdz IEYxQzEwMHMgVVNCIHN1cHBvcnQKPiA+IHNlcmllcyBbMV0uIFRoZXJlIGlzIG5vIHJlYWwgY29u ZmxpY3QsIGJ1dCB0aGUgbGN0ZWNoLXBpLmR0cyBmaWxlCj4gPiByZWZlcmVuY2VzIHRoZSBuZXcg VVNCIERUIG5vZGVzIGZyb20gdGhlIC5kdHNpLgo+ID4gCj4gPiBJIHB1dCBhIGdpdCByZXBvIHdp dGggYWxsIHRob3NlIHBhdGNoZXMgdXAgaGVyZToKPiA+IGh0dHBzOi8vZ2l0aHViLmNvbS9hcHJp dHplbC9saW51eC9jb21taXRzL2YxYzEwMHMtZGV2aWNlcy12Mgo+ID4gCj4gPiBGb3IgYSBjaGFu Z2Vsb2cgc2VlIGJlbG93Lgo+ID4gCj4gPiBbMV0KPiA+IGh0dHBzOi8vbG9yZS5rZXJuZWwub3Jn L2xpbnV4LWFybS1rZXJuZWwvMjAyMjExMDYxNTQ4MjYuNjY4Ny0xLWFuZHJlLnByenl3YQo+ID4g cmFAYXJtLmNvbS9ULyN0Cj4gPiAKPiA+ID09PT09PT09PT09PT09PT09Cj4gPiBUaGUgQWxsd2lu bmVyIEYxQzEwMHMgc2VyaWVzIG9mIFNvQ3Mgc2hhcmVzIG1hbnkgcGVyaXBoZXJhbHMgd2l0aCBv dGhlcgo+ID4gQWxsd2lubmVyIFNvQ3MuIFNpbmNlIHRoZXkgYXJlIGNvbXBhdGlibGUsIHdlIGNh biB1c2UgdGhlIGV4aXN0aW5nCj4gPiBkcml2ZXJzLCBhbmQganVzdCBuZWVkIHRvIGVuYWJsZSB0 aGUgZGV2aWNlcyBpbiB0aGUgRFQuCj4gPiAKPiA+IFRoaXMgc2VyaWVzIGFkZHMgdGhlIEkyQyBj b250cm9sbGVycywgdGhlIFBXTSBkZXZpY2UsIHRoZSBDSVIgKGluZnJhcmVkKQo+ID4gZGV2aWNl IGFuZCB0aGUgTFJBREMgKGFrYS4gS0VZQURDLCBsb3cgcmVzIEFEQykgdG8gdGhlIEYxQzEwMHMg LmR0c2ksIHNvCj4gPiBib2FyZHMgY2FuIGp1c3QgdXNlIHRoZW0gYnkgc2V0dGluZyAnc3RhdHVz ID0gIm9rYXkiOycuCj4gPiAKPiA+IFRoZSBvbmx5IHRoaW5nIG1pc3NpbmcgZHJpdmVyLXdpc2Ug aXMgdGhlIElSIG1vZCBjbG9jaywgd2hpY2ggd2FzIG5vdAo+ID4gbW9kZWxlZCBpbiBvdXIgQ0NV IGRyaXZlci4gUGF0Y2ggNC8xMCBmaXhlcyB0aGF0Lgo+ID4gCj4gPiBGb3IgZXZlcnkgZGV2aWNl IHRoZXJlIGlzIG9uZSBwYXRjaCB0aGF0IGFkZHMgdGhlIG5ldyBjb21wYXRpYmxlIHN0cmluZwo+ ID4gdG8gdGhlIERUIGJpbmRpbmcsIGFuZCBhbm90aGVyIHBhdGNoIHRvIGFkZCB0aGUgRFQgbm9k ZS4KPiA+IAo+ID4gVGhpcyBoYXMgYmVlbiB0ZXN0ZWQgb24gdGhlIExjdGVjaCBQaSBGMUMyMDBz IGJvYXJkLCBieToKPiA+IC0gQ29ubmVjdGluZyBhbiBMRUQgdG8gUEU2LCBhbmQgY29uZmlndXJp bmcgdGhpcyBhcyB0aGUgUFdNIHBpbiBpbiB0aGUgRFQuCj4gPiAgIERvaW5nIGEgc3dlZXAgb24g L3N5cy9jbGFzcy9wd20vcHdtMS9kdXR5X2N5Y2xlIG1hZGUgdGhlIExFRCBmYWRlIG91dC4KPiA+ IC0gQ29uZmlndXJpbmcgUEQwL1BEMTIgYXMgSTJDMCwgYW5kIGxldHRpbmcgaTJjLWRldGVjdCBm aW5kIHRoZSBvbi1ib2FyZAo+ID4gICBOUzIwMDkgSTJDIGNoaXAuCj4gPiAtIENvbm5lY3Rpbmcg dHdvIHJlc2lzdG9ycyB0byB0aGUgIkFEQyIgcGluLCBhbmQgY29uZmlndXJpbmcgdGhlbSBhcyB0 d28KPiA+ICAgYnV0dG9ucyBpbiB0aGUgRFQuIC9kZXYvaW5wdXQvZXZlbnQwIHByb3Blcmx5IHJl cG9ydGVkIGJ1dHRvbiBwcmVzc2VzLgo+ID4gLSBDb25uZWN0aW5nIGFuIGluZnJhcmVkIHJlY2Vp dmVyIHRvIFBFMTEsIGNvbmZpZ3VyZWQgYXMgQ0lSLgo+ID4gICBpci1rZXl0YWJsZSByZXBvcnRl ZCBrZXkgcHJlc3NlcyBvbiBhIHJlbW90ZSBjb250cm9sLgo+ID4gCj4gPiBBbGwgdGhvc2UgKGJh c2ljKSB0ZXN0cyB3ZXJlIHN1Y2Nlc3NmdWwsIGFuZCBwcm92ZSB0aGF0IHRoZSBwZXJpcGhlcmFs cwo+ID4gZG8gd29yayBhbmQgYXJlIGNvbXBhdGlibGUuCj4gPiAKPiA+IFRoZSBmaW5hbCB0aHJl ZSBwYXRjaGVzIGFkZCB0aGUgYmluZGluZyBkb2NzIGFuZCB0aGUgLmR0cyBmaWxlIGZvciB0aGUK PiA+IExjdGVjaCBQaSBGMUMyMDBzIGRldmVsb3BtZW50IGJvYXJkLgo+ID4gCj4gPiBQbGVhc2Ug aGF2ZSBhIGxvb2sgYW5kIHRlc3Qgb24geW91ciBoYXJkd2FyZSwgaWYgcG9zc2libGUuCj4gPiAK PiA+IENoZWVycywKPiA+IEFuZHJlCj4gPiAKPiA+IENoYW5nZWxvZyB2MSAuLi4gdjI6Cj4gPiAt IGRyb3BwZWQgZm9ybWVyIHBhdGNoIDMvOSBhbmQgOC85OiBhbHJlYWR5IGFwcGxpZWQKPiA+IC0g aW5jcmVhc2UgcmVnaXN0ZXIgZnJhbWUgc2l6ZSBpbiBEVCBmb3IgUFdNIGFuZCBMUkFEQwo+ID4g LSBkcm9wIEkyQzEgcGlucyBmcm9tIHBpbmN0cm9sbGVyIERUIG5vZGUKPiA+IC0gaW5jcmVhc2Ug SVIgbW9kIGNsb2NrIG11eCB0byAyIGJpdHMKPiA+IC0gZml4IG1pc3R5cGVkIGNvbW1hIGluIHZl bmRvciBwcmVmaXggbmFtZQo+ID4gLSBkcm9wIHVubmVlZGVkIG1tYzAgYW5kIHNwaTAgYWxpYXNl cyBmcm9tIExjdGVjaCBQaSBEVAo+ID4gLSBhZGQgL29taXQtaWYtbm8tcmVmLyB0YWcgdG8gVUFS VDEgcGlucwo+ID4gLSBhZGQgQUNLcyBhbmQgUmV2aWV3ZWQtYnkgdGFncwo+ID4gCj4gPiAKPiA+ IEFuZHJlIFByenl3YXJhICgxMCk6Cj4gPiAgIGR0LWJpbmRpbmdzOiBwd206IGFsbHdpbm5lcixz dW40aS1hMTA6IEFkZCBGMUMxMDBzIGNvbXBhdGlibGUKPiA+ICAgQVJNOiBkdHM6IHN1bml2OiBm MWMxMDBzOiBhZGQgUFdNIG5vZGUKPiA+ICAgQVJNOiBkdHM6IHN1bml2OiBmMWMxMDBzOiBhZGQg STJDIERUIG5vZGVzCj4gPiAgIGNsazogc3VueGktbmc6IGYxYzEwMHM6IEFkZCBJUiBtb2QgY2xv Y2sKPiA+ICAgZHQtYmluZGluZ3M6IG1lZGlhOiBJUjogQWRkIEYxQzEwMHMgSVIgY29tcGF0aWJs ZSBzdHJpbmcKPiA+ICAgQVJNOiBkdHM6IHN1bml2OiBmMWMxMDBzOiBhZGQgQ0lSIERUIG5vZGUK PiA+ICAgQVJNOiBkdHM6IHN1bml2OiBmMWMxMDBzOiBhZGQgTFJBREMgbm9kZQo+ID4gICBkdC1i aW5kaW5nczogdmVuZG9yLXByZWZpeGVzOiBhZGQgTGN0ZWNoIG5hbWUKPiA+ICAgZHQtYmluZGlu Z3M6IGFybTogc3VueGk6IGFkZCBjb21wYXRpYmxlIHN0cmluZ3MgZm9yIExjdGVjaCBQaQo+ID4g ICBBUk06IGR0czogc3VuaXY6IEFkZCBMY3RlY2ggUGkgRjFDMjAwcyBkZXZpY2V0cmVlCj4gPiAK PiA+ICAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0vc3VueGkueWFtbCAgICAgICAgfCAgNiAr Kwo+ID4gIC4uLi9tZWRpYS9hbGx3aW5uZXIsc3VuNGktYTEwLWlyLnlhbWwgICAgICAgICB8ICAx ICsKPiA+ICAuLi4vYmluZGluZ3MvcHdtL2FsbHdpbm5lcixzdW40aS1hMTAtcHdtLnlhbWwgfCAg NCArLQo+ID4gIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL3ZlbmRvci1wcmVmaXhlcy55YW1sICB8 ICAyICsKPiA+ICBhcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZSAgICAgICAgICAgICAgICAgICAg fCAgMSArCj4gPiAgYXJjaC9hcm0vYm9vdC9kdHMvc3VuaXYtZjFjMTAwcy5kdHNpICAgICAgICAg IHwgNzYgKysrKysrKysrKysrKysrKysrCj4gPiAgYXJjaC9hcm0vYm9vdC9kdHMvc3VuaXYtZjFj MjAwcy1sY3RlY2gtcGkuZHRzIHwgNzggKysrKysrKysrKysrKysrKysrKwo+ID4gIGRyaXZlcnMv Y2xrL3N1bnhpLW5nL2NjdS1zdW5pdi1mMWMxMDBzLmMgICAgICB8IDExICsrLQo+ID4gIGRyaXZl cnMvY2xrL3N1bnhpLW5nL2NjdS1zdW5pdi1mMWMxMDBzLmggICAgICB8ICAyICstCj4gPiAgaW5j bHVkZS9kdC1iaW5kaW5ncy9jbG9jay9zdW5pdi1jY3UtZjFjMTAwcy5oIHwgIDIgKwo+ID4gIDEw IGZpbGVzIGNoYW5nZWQsIDE4MCBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQo+ID4gIGNy ZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9ib290L2R0cy9zdW5pdi1mMWMyMDBzLWxjdGVjaC1w aS5kdHMKPiA+IAo+ID4gLS0KPiA+IDIuMzUuNSAgCj4gCj4gCgoKX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxp c3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZy YWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=