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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 128-20020a4a0d86000000b004805b00b2cdsm4299638oob.28.2022.11.14.17.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 17:46:11 -0800 (PST) Received: (nullmailer pid 3961451 invoked by uid 1000); Tue, 15 Nov 2022 01:46:13 -0000 Date: Mon, 14 Nov 2022 19:46:13 -0600 From: Rob Herring To: Biju Das Cc: Thierry Reding , Krzysztof Kozlowski , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Message-ID: <20221115014613.GA3959192-robh@kernel.org> References: <20221111192942.717137-1-biju.das.jz@bp.renesas.com> <20221111192942.717137-3-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221111192942.717137-3-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org On Fri, Nov 11, 2022 at 07:29:41PM +0000, Biju Das wrote: > RZ/G2L GPT IP supports output pin disable function by dead time > error and detecting short-circuits between output pins. > > Add documentation for the optional property renesas,poegs to > link a pair of GPT IOs with POEG. > > Signed-off-by: Biju Das > --- > v1->v2: > * removed quotes from ref > * Added maxItems and minItems for renesas,poegs property > * Added enums for gpt index > --- > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > index 620d5ae4ae30..5219032c60ee 100644 > --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > @@ -245,6 +245,28 @@ properties: > resets: > maxItems: 1 > > + renesas,poegs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + maxItems: 8 > + minItems: 1 I think you want these moved up a level with the 1st 'items'. It's 1-8 tuples, right? > + items: > + - description: phandle to POEG instance that serves the output disable > + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] > + description: | > + An index identifying pair of GPT channels. > + <0> : GPT channels 0 and 1 > + <1> : GPT channels 2 and 3 > + <2> : GPT channels 4 and 5 > + <3> : GPT channels 6 and 7 > + <4> : GPT channels 8 and 9 > + <5> : GPT channels 10 and 11 > + <6> : GPT channels 12 and 13 > + <7> : GPT channels 14 and 15 > + description: > + A list of phandle and channel index pair tuples to the POEGs that handle the > + output disable for the GPT channels. > + > required: > - compatible > - reg > @@ -375,4 +397,5 @@ examples: > power-domains = <&cpg>; > resets = <&cpg R9A07G044_GPT_RST_C>; > #pwm-cells = <2>; > + renesas,poegs = <&poeggd 4>; > }; > -- > 2.25.1 > >