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[2603:6081:7b00:6400:29a0:35f:b06a:235e]) by smtp.gmail.com with ESMTPSA id bk23-20020a05620a1a1700b006ce580c2663sm6387502qkb.35.2022.11.20.06.09.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Nov 2022 06:09:08 -0800 (PST) From: Tom Rini To: u-boot@lists.denx.de Subject: [PoC 171/241] global: Migrate CONFIG_SAR_REG to CFG Date: Sun, 20 Nov 2022 09:08:01 -0500 Message-Id: <20221120140829.3057894-62-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221120140829.3057894-1-trini@konsulko.com> References: <20221120135520.3057773-4-trini@konsulko.com> <20221120140829.3057894-1-trini@konsulko.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Tom Rini --- arch/arm/mach-kirkwood/include/mach/kw88f6281.h | 2 +- arch/arm/mach-kirkwood/include/mach/soc.h | 2 +- arch/arm/mach-mvebu/cpu.c | 4 ++-- arch/arm/mach-mvebu/include/mach/soc.h | 12 ++++++------ scripts/config_whitelist.txt | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index 7f8e156a6bdc..67f0b3ec6772 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000) #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h index 5f545c6f4349..4a7efc50f67a 100644 --- a/arch/arm/mach-kirkwood/include/mach/soc.h +++ b/arch/arm/mach-kirkwood/include/mach/soc.h @@ -62,7 +62,7 @@ #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE -#define CONFIG_SAR_REG (KW_MPP_BASE + 0x0030) +#define CFG_SAR_REG (KW_MPP_BASE + 0x0030) #if defined (CONFIG_KW88F6281) #include diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9139df1ae248..329d13691f0e 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -83,7 +83,7 @@ u32 get_boot_device(void) /* * Now check the SAR register for the strapped boot-device */ - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); switch (boot_device) { @@ -197,7 +197,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */ #else - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ #endif freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; #if defined(SAR2_CPU_FREQ_MASK) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1210d26c7461..6edd2e2d79c7 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -134,7 +134,7 @@ #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) +#define CFG_SAR_REG (MVEBU_REGISTER(0xe8200)) #define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define SAR_CPU_FREQ_OFFS 17 @@ -146,11 +146,11 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18600)) #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -169,11 +169,11 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ -#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CFG_SAR_REG (MBUS_DFX_BASE + 0xf8200) #define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define SAR_CPU_FREQ_OFFS 18 @@ -191,7 +191,7 @@ #define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define SAR_CPU_FREQ_OFFS 21 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ed50a507f270..bdb3b68f8c80 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -180,7 +180,7 @@ CFG_SANDBOX_ARCH CFG_SANDBOX_SPI_MAX_BUS CFG_SANDBOX_SPI_MAX_CS CFG_SAR2_REG -CONFIG_SAR_REG +CFG_SAR_REG CONFIG_SCIF_A CONFIG_SCSI_DEV_LIST CONFIG_SC_TIMER_CLK -- 2.25.1