From: Ard Biesheuvel <ardb@kernel.org>
To: qemu-devel@nongnu.org
Cc: "Ard Biesheuvel" <ardb@kernel.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PATCH] target/arm: Use signed quantity to represent VMSAv8-64 translation level
Date: Mon, 21 Nov 2022 18:43:26 +0100 [thread overview]
Message-ID: <20221121174326.68520-1-ardb@kernel.org> (raw)
The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity, and should
be typed as such. So turn it from uint32_t into int32_t.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
target/arm/ptw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3745ac9723..6d6992580a 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1172,7 +1172,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
ARMCPU *cpu = env_archcpu(env);
ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
bool is_secure = ptw->in_secure;
- uint32_t level;
+ int32_t level;
ARMVAParameters param;
uint64_t ttbr;
hwaddr descaddr, indexmask, indexmask_grainsize;
--
2.35.1
next reply other threads:[~2022-11-21 17:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-21 17:43 Ard Biesheuvel [this message]
2022-11-21 18:51 ` [PATCH] target/arm: Use signed quantity to represent VMSAv8-64 translation level Peter Maydell
2022-11-21 19:02 ` Ard Biesheuvel
2022-11-22 13:20 ` Peter Maydell
2022-11-22 15:49 ` Ard Biesheuvel
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