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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
	<terry.bowman@amd.com>, <bhelgaas@google.com>,
	<dave.jiang@intel.com>, <nvdimm@lists.linux.dev>
Subject: Re: [PATCH v4 11/12] tools/testing/cxl: Add an RCH topology
Date: Tue, 29 Nov 2022 12:52:26 +0000	[thread overview]
Message-ID: <20221129125226.00004b33@Huawei.com> (raw)
In-Reply-To: <6385392d6bd_3cbe02945b@dwillia2-xfh.jf.intel.com.notmuch>

On Mon, 28 Nov 2022 14:41:49 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> Alison Schofield wrote:
> > On Thu, Nov 24, 2022 at 10:35:38AM -0800, Dan Williams wrote:  
> > > In an RCH topology a CXL host-bridge as Root Complex Integrated Endpoint
> > > the represents the memory expander. Unlike a VH topology there is no
> > > CXL/PCIE Root Port that host the endpoint. The CXL subsystem maps this
> > > as the CXL root object (ACPI0017 on ACPI based systems) targeting the
> > > host-bridge as a dport, per usual, but then that dport directly hosts
> > > the endpoint port.
> > > 
> > > Mock up that configuration with a 4th host-bridge that has a 'cxl_rcd'
> > > device instance as its immediate child.
> > >   
> > 
> > Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> > 
> > How can this host bridge and device be used?  
> 
> Answering the direct question... it's not good for much more than
> testing enumeration. The expectation is that RCH hosts will be
> configured by BIOS and most likely Linux driver only ever needs to read
> the configuration, not change it.  So most of the excitement from a
> cxl_test perspective is in the enumeration. The rest of the RCH enabling
> will be for error handling for errors that impact regions set up by
> BIOS. That testing will need hardware, or QEMU, but I do not expect RCH
> topologies to show up in QEMU any time soon, if ever.

I wasn't planning on QEMU support, but if someone wants to do it I'll be
happy to review!  Patches welcome etc.  As Dan says, it'll be a job for BIOS
configuration and so far we don't have a suitable BIOS to run against
the QEMU emulation - there is code for ARM's own models (FVP) as talked about
at Plumbers CXL UConf, but I don't know of anyone looking at getting that
up and running on top of QEMU yet.  That would be best done first on CXL 2.0+
but once it is place, a full setup for RCH would be possible.

Given there is hardware and new features aren't going to be built on RCH
topologies, I'd guess no one will care enough to write QEMU emulation
any time soon.

Jonathan

  reply	other threads:[~2022-11-29 12:52 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 18:34 [PATCH v4 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Dan Williams
2022-11-24 18:34 ` [PATCH v4 01/12] cxl/acpi: Simplify cxl_nvdimm_bridge probing Dan Williams
2022-11-24 18:34 ` [PATCH v4 02/12] cxl/region: Drop redundant pmem region release handling Dan Williams
2022-11-24 18:34 ` [PATCH v4 03/12] cxl/pmem: Refactor nvdimm device registration, delete the workqueue Dan Williams
2022-11-25 15:01   ` Jonathan Cameron
2022-11-25 23:58     ` Dan Williams
2022-11-26  0:49   ` [PATCH v5 " Dan Williams
2022-11-24 18:34 ` [PATCH v4 04/12] cxl/pmem: Remove the cxl_pmem_wq and related infrastructure Dan Williams
2022-11-24 18:35 ` [PATCH v4 05/12] cxl/acpi: Move rescan to the workqueue Dan Williams
2022-11-24 18:35 ` [PATCH v4 06/12] tools/testing/cxl: Make mock CEDT parsing more robust Dan Williams
2022-11-28 11:13   ` Robert Richter
2022-11-28 18:20   ` Alison Schofield
2022-11-28 22:10     ` Dan Williams
2022-11-24 18:35 ` [PATCH v4 07/12] cxl/ACPI: Register CXL host ports by bridge device Dan Williams
2022-11-28 11:45   ` Robert Richter
2022-11-24 18:35 ` [PATCH v4 08/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Dan Williams
2022-11-28 14:32   ` Robert Richter
2022-11-28 21:58     ` Dan Williams
2022-11-28 22:56       ` Robert Richter
2022-11-29  0:10         ` Dan Williams
2022-11-30 14:43       ` Robert Richter
2022-11-24 18:35 ` [PATCH v4 09/12] cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_mem Dan Williams
2022-11-28 19:50   ` Robert Richter
2022-11-28 20:35     ` Robert Richter
2022-11-28 23:42     ` Dan Williams
2022-11-29 20:52       ` Robert Richter
2022-11-24 18:35 ` [PATCH v4 10/12] cxl/port: Add RCD endpoint port enumeration Dan Williams
2022-11-28 16:28   ` Dave Jiang
2022-11-28 18:20     ` Dan Williams
2022-11-28 23:06   ` Robert Richter
2022-11-29  0:25     ` Dan Williams
2022-11-29 21:22       ` Robert Richter
2022-11-30 20:39         ` Dan Williams
2022-12-01 15:23           ` Robert Richter
2022-12-01 22:18             ` Robert Richter
2022-12-01 22:43   ` Robert Richter
2022-12-01 23:48     ` Dan Williams
2022-11-24 18:35 ` [PATCH v4 11/12] tools/testing/cxl: Add an RCH topology Dan Williams
2022-11-28 19:26   ` Alison Schofield
2022-11-28 22:28     ` Dan Williams
2022-11-28 22:41     ` Dan Williams
2022-11-29 12:52       ` Jonathan Cameron [this message]
2022-11-29 20:49   ` Robert Richter
2022-11-30 20:24     ` Dan Williams
2022-11-24 18:35 ` [PATCH v4 12/12] cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support Dan Williams
2022-11-30  8:16   ` Robert Richter
2022-11-30 21:02     ` Dan Williams
2022-11-29 21:26 ` [PATCH v4 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-11-30 20:59   ` Dan Williams
2022-12-01 22:59     ` Robert Richter
2022-11-30 17:14 ` Robert Richter

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