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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v1] Xen: Enable compilation when PADDR_BITS == BITS_PER_LONG Date: Thu, 1 Dec 2022 10:03:09 +0000 Message-ID: <20221201100309.2385-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT026:EE_|SN7PR12MB8130:EE_ X-MS-Office365-Filtering-Correlation-Id: b41815ac-4a69-4a2a-8b7d-08dad3834817 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sLE0xPty9CyeII0Jb9InV+MwYhfvuuV0horP8Fm6eTumTfOFmdu79M4xaPsB4MyK8k1gYMoL4zoqEhcxI329ClpkHbHE3T3QSDYifvmVF6Q725VkITTZP3bwYCYnrwdWHkBJPuXy5H/QwLUzbzzU5i9jwM+Dn4KfSY+4jh8jxdhr6ylZZ8AQ2tDZKWNYSpSn9YtZGBdC+rIO7YPBHFz2qDacI96SCwQT5hYr2ocYwXhOIKVw4RGq+Arlhq58aQKakYBFd5/U2QpYQvRgZuAVlvf6Y2cFfGUvn6IZ99JCXdSIFitdoWsd+zVXJ5Pr19rEc5PB1QRz0dO+GelaHRfr32CK7sOMzFNni4VyXJWLxd6oJJwPhzzlgT2w+GFiyMicC0HbYz1oy0R4eQ8SdAuOwN9Cjie+SYrp9zZTjP3XKGsSrAB07AUUkAReIQw1qO6KSVbXCv3O/YcTK+UJ5rQhVGROPzXm3z8ZRBI44vc89eFB6DmpbEMXE7XWSpMPj1yH2l4zUsgdFgP5Yl6LrU1nJ9yFp6jsYAtcPbIqblpuXqVWqJMrR3ZPK05ctLWXZ1s5mIMwy/vT0mlDXY+FlSjBSCxnQdjmi/VG13EBVFLvNmr/5VDsl8KY+YdKFe/SmUBODaXUSMcJtS/feXTR3hfzoJicT8h9G6/kr6zxawEUoZ0EZBpAkjLgHE1ngmT7sZnxrBd36IPbk2VUt588HX0QklgB6OtHmBHnhvIf69KuJok= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199015)(46966006)(40470700004)(36840700001)(316002)(478600001)(26005)(103116003)(186003)(36756003)(1076003)(2616005)(54906003)(6916009)(356005)(81166007)(36860700001)(40480700001)(40460700003)(47076005)(86362001)(82740400003)(426003)(336012)(82310400005)(83380400001)(6666004)(4326008)(70586007)(8676002)(70206006)(8936002)(5660300002)(7416002)(41300700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 10:03:22.9244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b41815ac-4a69-4a2a-8b7d-08dad3834817 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8130 It is possible for a pointer to represent physical memory of the same size. In other words, a 32 bit pointer can represent 32 bit addressable physical memory. Thus, issue a compilation failure only when the count of physical address bits is greater than BITS_PER_LONG (ie count of bits in void*). Signed-off-by: Ayan Kumar Halder --- Currently this change will not have any impact on the existing architectures. The following table illustrates PADDR_BITS vs BITS_PER_LONG of different archs ------------------------------------------------ | Arch | PADDR_BITS | BITS_PER_LONG | ------------------------------------------------ | Arm_64 | 48 | 64 | | Arm_32 | 40 | 32 | | RISCV_64 | Don't know | 64 | | x86 | 52 | 64 | ------------------------------------------------- However, this will change when we introduce a platform (For eg Cortex-R52) which supports 32 bit physical address and BITS_PER_LONG. Thus, I have introduced this change as I don't see it causing a regression on any of the supported platforms. xen/common/page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 62afb07bc6..cd390a0956 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -2245,7 +2245,7 @@ void __init xenheap_max_mfn(unsigned long mfn) { ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); - BUILD_BUG_ON(PADDR_BITS >= BITS_PER_LONG); + BUILD_BUG_ON(PADDR_BITS > BITS_PER_LONG); xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } -- 2.17.1