From: Andre Przywara <andre.przywara@arm.com>
To: Samuel Holland <samuel@sholland.org>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>,
Anatolij Gustschin <agust@denx.de>,
Jagan Teki <jagan@amarulasolutions.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
u-boot@lists.denx.de
Subject: Re: [PATCH 1/5] clk: sunxi: Add DE2 display-related clocks/resets
Date: Sat, 3 Dec 2022 17:14:14 +0000 [thread overview]
Message-ID: <20221203171414.18ff93ee@slackpad.lan> (raw)
In-Reply-To: <20221128070229.4394-2-samuel@sholland.org>
On Mon, 28 Nov 2022 01:02:24 -0600
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> Add clock/reset definitions for display-related peripherals, including
> the display engine, TCONs, and DSI and HDMI encoders, so those drivers
> can be converted to DM clock consumers instead of directly manipulating
> the CCU registers.
Thanks for that. Compared all register addresses and bit locations
against their respective manual.
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> drivers/clk/sunxi/clk_a64.c | 22 ++++++++++++++++++++++
> drivers/clk/sunxi/clk_a83t.c | 22 ++++++++++++++++++++++
> drivers/clk/sunxi/clk_h3.c | 17 +++++++++++++++++
> drivers/clk/sunxi/clk_h6.c | 21 +++++++++++++++++++++
> drivers/clk/sunxi/clk_h616.c | 21 +++++++++++++++++++++
> drivers/clk/sunxi/clk_r40.c | 29 +++++++++++++++++++++++++++++
> drivers/clk/sunxi/clk_v3s.c | 9 +++++++++
> 7 files changed, 141 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 8c81b1ac453..136ba89293d 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -16,6 +16,7 @@
> static const struct ccu_clk_gate a64_gates[] = {
> [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
>
> + [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)),
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -28,6 +29,11 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
> [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_TCON0] = GATE(0x064, BIT(3)),
> + [CLK_BUS_TCON1] = GATE(0x064, BIT(4)),
> + [CLK_BUS_HDMI] = GATE(0x064, BIT(11)),
> + [CLK_BUS_DE] = GATE(0x064, BIT(12)),
> +
> [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
>
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> @@ -48,6 +54,15 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
> [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
> [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
> +
> + [CLK_DE] = GATE(0x104, BIT(31)),
> + [CLK_TCON0] = GATE(0x118, BIT(31)),
> + [CLK_TCON1] = GATE(0x11c, BIT(31)),
> +
> + [CLK_HDMI] = GATE(0x150, BIT(31)),
> + [CLK_HDMI_DDC] = GATE(0x154, BIT(31)),
> +
> + [CLK_DSI_DPHY] = GATE(0x168, BIT(15)),
> };
>
> static const struct ccu_reset a64_resets[] = {
> @@ -55,6 +70,7 @@ static const struct ccu_reset a64_resets[] = {
> [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
> [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
>
> + [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)),
> [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
> [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
> [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
> @@ -67,6 +83,12 @@ static const struct ccu_reset a64_resets[] = {
> [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
> [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
>
> + [RST_BUS_TCON0] = RESET(0x2c4, BIT(3)),
> + [RST_BUS_TCON1] = RESET(0x2c4, BIT(4)),
> + [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
> + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
> + [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
> +
> [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
> index 3562da61d14..d5af37b3d78 100644
> --- a/drivers/clk/sunxi/clk_a83t.c
> +++ b/drivers/clk/sunxi/clk_a83t.c
> @@ -14,6 +14,7 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate a83t_gates[] = {
> + [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)),
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -25,6 +26,11 @@ static struct ccu_clk_gate a83t_gates[] = {
> [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_TCON0] = GATE(0x064, BIT(4)),
> + [CLK_BUS_TCON1] = GATE(0x064, BIT(5)),
> + [CLK_BUS_HDMI] = GATE(0x064, BIT(11)),
> + [CLK_BUS_DE] = GATE(0x064, BIT(12)),
> +
> [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
>
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> @@ -44,6 +50,15 @@ static struct ccu_clk_gate a83t_gates[] = {
> [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
> [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
> [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
> +
> + [CLK_TCON0] = GATE(0x118, BIT(31)),
> + [CLK_TCON1] = GATE(0x11c, BIT(31)),
> +
> + [CLK_HDMI] = GATE(0x150, BIT(31)),
> + [CLK_HDMI_SLOW] = GATE(0x154, BIT(31)),
> +
> + [CLK_MIPI_DSI0] = GATE(0x168, BIT(31)),
> + [CLK_MIPI_DSI1] = GATE(0x16c, BIT(31)),
> };
>
> static struct ccu_reset a83t_resets[] = {
> @@ -51,6 +66,7 @@ static struct ccu_reset a83t_resets[] = {
> [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
> [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
>
> + [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)),
> [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
> [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
> [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
> @@ -62,6 +78,12 @@ static struct ccu_reset a83t_resets[] = {
> [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
> [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
>
> + [RST_BUS_TCON0] = RESET(0x2c4, BIT(4)),
> + [RST_BUS_TCON1] = RESET(0x2c4, BIT(5)),
> + [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
> + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
> + [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
> +
> [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
> index 17ab3b5c278..213ab510ed5 100644
> --- a/drivers/clk/sunxi/clk_h3.c
> +++ b/drivers/clk/sunxi/clk_h3.c
> @@ -32,6 +32,11 @@ static struct ccu_clk_gate h3_gates[] = {
> [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
> [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
>
> + [CLK_BUS_TCON0] = GATE(0x064, BIT(3)),
> + [CLK_BUS_TCON1] = GATE(0x064, BIT(4)),
> + [CLK_BUS_HDMI] = GATE(0x064, BIT(11)),
> + [CLK_BUS_DE] = GATE(0x064, BIT(12)),
> +
> [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
>
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> @@ -55,6 +60,12 @@ static struct ccu_clk_gate h3_gates[] = {
> [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
> [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
> [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
> +
> + [CLK_DE] = GATE(0x104, BIT(31)),
> + [CLK_TCON0] = GATE(0x118, BIT(31)),
> +
> + [CLK_HDMI] = GATE(0x150, BIT(31)),
> + [CLK_HDMI_DDC] = GATE(0x154, BIT(31)),
> };
>
> static struct ccu_reset h3_resets[] = {
> @@ -79,6 +90,12 @@ static struct ccu_reset h3_resets[] = {
> [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
> [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
>
> + [RST_BUS_TCON0] = RESET(0x2c4, BIT(3)),
> + [RST_BUS_TCON1] = RESET(0x2c4, BIT(4)),
> + [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
> + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
> + [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
> +
> [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
>
> [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index 041bc5e80ed..24eb9725dbc 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -18,6 +18,9 @@ static struct ccu_clk_gate h6_gates[] = {
>
> [CLK_APB1] = GATE_DUMMY,
>
> + [CLK_DE] = GATE(0x600, BIT(31)),
> + [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> @@ -55,9 +58,21 @@ static struct ccu_clk_gate h6_gates[] = {
> [CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)),
> [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
> [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
> +
> + [CLK_HDMI] = GATE(0xb00, BIT(31)),
> + [CLK_HDMI_SLOW] = GATE(0xb04, BIT(31)),
> + [CLK_HDMI_CEC] = GATE(0xb10, BIT(31)),
> + [CLK_BUS_HDMI] = GATE(0xb1c, BIT(0)),
> + [CLK_BUS_TCON_TOP] = GATE(0xb5c, BIT(0)),
> + [CLK_TCON_LCD0] = GATE(0xb60, BIT(31)),
> + [CLK_BUS_TCON_LCD0] = GATE(0xb7c, BIT(0)),
> + [CLK_TCON_TV0] = GATE(0xb80, BIT(31)),
> + [CLK_BUS_TCON_TV0] = GATE(0xb9c, BIT(0)),
> };
>
> static struct ccu_reset h6_resets[] = {
> + [RST_BUS_DE] = RESET(0x60c, BIT(16)),
> +
> [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
> [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
> [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
> @@ -89,6 +104,12 @@ static struct ccu_reset h6_resets[] = {
> [RST_BUS_XHCI] = RESET(0xa8c, BIT(21)),
> [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
> [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
> +
> + [RST_BUS_HDMI] = RESET(0xb1c, BIT(16)),
> + [RST_BUS_HDMI_SUB] = RESET(0xb1c, BIT(17)),
> + [RST_BUS_TCON_TOP] = RESET(0xb5c, BIT(16)),
> + [RST_BUS_TCON_LCD0] = RESET(0xb7c, BIT(16)),
> + [RST_BUS_TCON_TV0] = RESET(0xb9c, BIT(16)),
> };
>
> const struct ccu_desc h6_ccu_desc = {
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index 964636d7281..88d6bf3420d 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -17,6 +17,9 @@ static struct ccu_clk_gate h616_gates[] = {
>
> [CLK_APB1] = GATE_DUMMY,
>
> + [CLK_DE] = GATE(0x600, BIT(31)),
> + [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
> +
> [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
> @@ -64,9 +67,21 @@ static struct ccu_clk_gate h616_gates[] = {
> [CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
> [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
> [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
> +
> + [CLK_HDMI] = GATE(0xb00, BIT(31)),
> + [CLK_HDMI_SLOW] = GATE(0xb04, BIT(31)),
> + [CLK_HDMI_CEC] = GATE(0xb10, BIT(31)),
> + [CLK_BUS_HDMI] = GATE(0xb1c, BIT(0)),
> + [CLK_BUS_TCON_TOP] = GATE(0xb5c, BIT(0)),
> + [CLK_TCON_TV0] = GATE(0xb80, BIT(31)),
> + [CLK_TCON_TV1] = GATE(0xb84, BIT(31)),
> + [CLK_BUS_TCON_TV0] = GATE(0xb9c, BIT(0)),
> + [CLK_BUS_TCON_TV1] = GATE(0xb9c, BIT(1)),
> };
>
> static struct ccu_reset h616_resets[] = {
> + [RST_BUS_DE] = RESET(0x60c, BIT(16)),
> +
> [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
> [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
> [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
> @@ -107,6 +122,12 @@ static struct ccu_reset h616_resets[] = {
> [RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
> [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
> [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
> +
> + [RST_BUS_HDMI] = RESET(0xb1c, BIT(16)),
> + [RST_BUS_HDMI_SUB] = RESET(0xb1c, BIT(17)),
> + [RST_BUS_TCON_TOP] = RESET(0xb5c, BIT(16)),
> + [RST_BUS_TCON_TV0] = RESET(0xb9c, BIT(16)),
> + [RST_BUS_TCON_TV1] = RESET(0xb9c, BIT(17)),
> };
>
> const struct ccu_desc h616_ccu_desc = {
> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
> index ef743d65b7f..630e80d2b4e 100644
> --- a/drivers/clk/sunxi/clk_r40.c
> +++ b/drivers/clk/sunxi/clk_r40.c
> @@ -14,6 +14,7 @@
> #include <linux/bitops.h>
>
> static struct ccu_clk_gate r40_gates[] = {
> + [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)),
> [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
> [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
> [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
> @@ -30,7 +31,15 @@ static struct ccu_clk_gate r40_gates[] = {
> [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
> [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
>
> + [CLK_BUS_HDMI0] = GATE(0x064, BIT(10)),
> + [CLK_BUS_HDMI1] = GATE(0x064, BIT(11)),
> + [CLK_BUS_DE] = GATE(0x064, BIT(12)),
> [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
> + [CLK_BUS_TCON_LCD0] = GATE(0x064, BIT(26)),
> + [CLK_BUS_TCON_LCD1] = GATE(0x064, BIT(27)),
> + [CLK_BUS_TCON_TV0] = GATE(0x064, BIT(28)),
> + [CLK_BUS_TCON_TV1] = GATE(0x064, BIT(29)),
> + [CLK_BUS_TCON_TOP] = GATE(0x064, BIT(30)),
>
> [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
>
> @@ -59,6 +68,17 @@ static struct ccu_clk_gate r40_gates[] = {
> [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
> [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
> [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
> +
> + [CLK_DE] = GATE(0x104, BIT(31)),
> + [CLK_TCON_LCD0] = GATE(0x110, BIT(31)),
> + [CLK_TCON_LCD1] = GATE(0x114, BIT(31)),
> + [CLK_TCON_TV0] = GATE(0x118, BIT(31)),
> + [CLK_TCON_TV1] = GATE(0x11c, BIT(31)),
> +
> + [CLK_HDMI] = GATE(0x150, BIT(31)),
> + [CLK_HDMI_SLOW] = GATE(0x154, BIT(31)),
> +
> + [CLK_DSI_DPHY] = GATE(0x168, BIT(15)),
> };
>
> static struct ccu_reset r40_resets[] = {
> @@ -66,6 +86,7 @@ static struct ccu_reset r40_resets[] = {
> [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
> [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
>
> + [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)),
> [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
> [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
> [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
> @@ -82,7 +103,15 @@ static struct ccu_reset r40_resets[] = {
> [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
> [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
>
> + [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
> + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
> + [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
> [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
> + [RST_BUS_TCON_LCD0] = RESET(0x2c4, BIT(26)),
> + [RST_BUS_TCON_LCD1] = RESET(0x2c4, BIT(27)),
> + [RST_BUS_TCON_TV0] = RESET(0x2c4, BIT(28)),
> + [RST_BUS_TCON_TV1] = RESET(0x2c4, BIT(29)),
> + [RST_BUS_TCON_TOP] = RESET(0x2c4, BIT(30)),
>
> [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index f2fd11eac2c..6524c13540e 100644
> --- a/drivers/clk/sunxi/clk_v3s.c
> +++ b/drivers/clk/sunxi/clk_v3s.c
> @@ -20,6 +20,9 @@ static struct ccu_clk_gate v3s_gates[] = {
> [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
> [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
>
> + [CLK_BUS_TCON0] = GATE(0x064, BIT(4)),
> + [CLK_BUS_DE] = GATE(0x064, BIT(12)),
> +
> [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
>
> [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> @@ -31,6 +34,9 @@ static struct ccu_clk_gate v3s_gates[] = {
> [CLK_SPI0] = GATE(0x0a0, BIT(31)),
>
> [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
> +
> + [CLK_DE] = GATE(0x104, BIT(31)),
> + [CLK_TCON0] = GATE(0x118, BIT(31)),
> };
>
> static struct ccu_reset v3s_resets[] = {
> @@ -42,6 +48,9 @@ static struct ccu_reset v3s_resets[] = {
> [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
> [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
>
> + [RST_BUS_TCON0] = RESET(0x2c4, BIT(4)),
> + [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
> +
> [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
next prev parent reply other threads:[~2022-12-03 17:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 7:02 [PATCH 0/5] video: sunxi: dw-hdmi: Partial OF conversion Samuel Holland
2022-11-28 7:02 ` [PATCH 1/5] clk: sunxi: Add DE2 display-related clocks/resets Samuel Holland
2022-12-03 17:14 ` Andre Przywara [this message]
2022-11-28 7:02 ` [PATCH 2/5] video: sunxi: dw-hdmi: Probe driver by compatible Samuel Holland
2022-12-03 17:14 ` Andre Przywara
2022-11-28 7:02 ` [PATCH 3/5] video: sunxi: dw-hdmi: Read address from DT node Samuel Holland
2023-01-23 1:09 ` Andre Przywara
2022-11-28 7:02 ` [PATCH 4/5] video: sunxi: dw-hdmi: Use DM for clock gates and resets Samuel Holland
2023-01-23 0:47 ` Andre Przywara
2022-11-28 7:02 ` [PATCH 5/5] video: sunxi: dw-hdmi: Use DM for HVCC regulator Samuel Holland
2023-01-23 1:10 ` Andre Przywara
2022-12-03 9:48 ` [PATCH 0/5] video: sunxi: dw-hdmi: Partial OF conversion Jernej Škrabec
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