From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: thuth@redhat.com, iii@linux.ibm.com
Subject: [PATCH v4 01/27] tcg/s390x: Use register pair allocation for div and mulu2
Date: Thu, 8 Dec 2022 20:05:04 -0600 [thread overview]
Message-ID: <20221209020530.396391-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20221209020530.396391-1-richard.henderson@linaro.org>
Previously we hard-coded R2 and R3.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 4 ++--
tcg/s390x/tcg-target-con-str.h | 8 +------
tcg/s390x/tcg-target.c.inc | 43 +++++++++++++++++++++++++---------
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 426dd92e51..00ba727b70 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -29,8 +29,8 @@ C_O1_I2(v, v, v)
C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
-C_O2_I2(b, a, 0, r)
-C_O2_I3(b, a, 0, 1, r)
+C_O2_I2(o, m, 0, r)
+C_O2_I3(o, m, 0, 1, r)
C_O2_I4(r, r, 0, 1, rA, r)
C_O2_I4(r, r, 0, 1, ri, r)
C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h
index 8bb0358ae5..76446aecae 100644
--- a/tcg/s390x/tcg-target-con-str.h
+++ b/tcg/s390x/tcg-target-con-str.h
@@ -11,13 +11,7 @@
REGS('r', ALL_GENERAL_REGS)
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
REGS('v', ALL_VECTOR_REGS)
-/*
- * A (single) even/odd pair for division.
- * TODO: Add something to the register allocator to allow
- * this kind of regno+1 pairing to be done more generally.
- */
-REGS('a', 1u << TCG_REG_R2)
-REGS('b', 1u << TCG_REG_R3)
+REGS('o', 0xaaaa) /* odd numbered general regs */
/*
* Define constraint letters for constants:
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index b9ba7b605e..cb00bb6999 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2264,10 +2264,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_div2_i32:
- tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RR, DR, args[1], args[4]);
break;
case INDEX_op_divu2_i32:
- tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DLR, args[1], args[4]);
break;
case INDEX_op_shl_i32:
@@ -2521,17 +2529,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_div2_i64:
- /* ??? We get an unnecessary sign-extension of the dividend
- into R3 with this definition, but as we do in fact always
- produce both quotient and remainder using INDEX_op_div_i64
- instead requires jumping through even more hoops. */
- tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
+ /*
+ * ??? We get an unnecessary sign-extension of the dividend
+ * into op0 with this definition, but as we do in fact always
+ * produce both quotient and remainder using INDEX_op_div_i64
+ * instead requires jumping through even more hoops.
+ */
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DSGR, args[1], args[4]);
break;
case INDEX_op_divu2_i64:
- tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert(args[1] == args[3]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, DLGR, args[1], args[4]);
break;
case INDEX_op_mulu2_i64:
- tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
+ tcg_debug_assert(args[0] == args[2]);
+ tcg_debug_assert((args[1] & 1) == 0);
+ tcg_debug_assert(args[0] == args[1] + 1);
+ tcg_out_insn(s, RRE, MLGR, args[1], args[3]);
break;
case INDEX_op_shl_i64:
@@ -3226,10 +3247,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- return C_O2_I3(b, a, 0, 1, r);
+ return C_O2_I3(o, m, 0, 1, r);
case INDEX_op_mulu2_i64:
- return C_O2_I2(b, a, 0, r);
+ return C_O2_I2(o, m, 0, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
--
2.34.1
next prev parent reply other threads:[~2022-12-09 2:08 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-09 2:05 [PATCH v4 00/27] tcg/s390x: misc patches Richard Henderson
2022-12-09 2:05 ` Richard Henderson [this message]
2022-12-09 2:05 ` [PATCH v4 02/27] tcg/s390x: Remove TCG_REG_TB Richard Henderson
2022-12-09 2:05 ` [PATCH v4 03/27] tcg/s390x: Always set TCG_TARGET_HAS_direct_jump Richard Henderson
2022-12-12 21:51 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 04/27] tcg/s390x: Remove USE_LONG_BRANCHES Richard Henderson
2022-12-12 21:52 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 05/27] tcg/s390x: Check for long-displacement facility at startup Richard Henderson
2022-12-12 21:54 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 06/27] tcg/s390x: Check for extended-immediate " Richard Henderson
2022-12-12 22:17 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 07/27] tcg/s390x: Check for general-instruction-extension " Richard Henderson
2022-12-12 22:21 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 08/27] tcg/s390x: Check for load-on-condition " Richard Henderson
2022-12-12 22:26 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 09/27] tcg/s390x: Remove FAST_BCR_SER facility check Richard Henderson
2022-12-12 22:08 ` Philippe Mathieu-Daudé
2022-12-09 2:05 ` [PATCH v4 10/27] tcg/s390x: Remove DISTINCT_OPERANDS " Richard Henderson
2022-12-12 22:29 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 11/27] tcg/s390x: Use LARL+AGHI for odd addresses Richard Henderson
2022-12-09 2:05 ` [PATCH v4 12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats Richard Henderson
2022-12-09 2:05 ` [PATCH v4 13/27] tcg/s390x: Distinguish RIE formats Richard Henderson
2022-12-09 2:05 ` [PATCH v4 14/27] tcg/s390x: Support MIE2 multiply single instructions Richard Henderson
2022-12-09 2:05 ` [PATCH v4 15/27] tcg/s390x: Support MIE2 MGRK instruction Richard Henderson
2022-12-09 2:05 ` [PATCH v4 16/27] tcg/s390x: Issue XILF directly for xor_i32 Richard Henderson
2022-12-12 22:30 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64 Richard Henderson
2022-12-12 22:41 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 18/27] tcg/s390x: Tighten constraints for and_i64 Richard Henderson
2022-12-12 22:57 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 19/27] tcg/s390x: Support MIE3 logical operations Richard Henderson
2022-12-09 2:05 ` [PATCH v4 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond Richard Henderson
2022-12-09 2:05 ` [PATCH v4 21/27] tcg/s390x: Generalize movcond implementation Richard Henderson
2022-12-09 2:05 ` [PATCH v4 22/27] tcg/s390x: Support SELGR instruction in movcond Richard Henderson
2022-12-09 2:05 ` [PATCH v4 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz Richard Henderson
2022-12-09 2:05 ` [PATCH v4 24/27] tcg/s390x: Implement ctpop operation Richard Henderson
2022-12-09 2:05 ` [PATCH v4 25/27] tcg/s390x: Tighten constraints for 64-bit compare Richard Henderson
2022-12-13 16:25 ` Ilya Leoshkevich
2022-12-13 16:43 ` Richard Henderson
2022-12-13 17:01 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 26/27] tcg/s390x: Cleanup tcg_out_movi Richard Henderson
2022-12-13 16:29 ` Ilya Leoshkevich
2022-12-09 2:05 ` [PATCH v4 27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi Richard Henderson
2022-12-13 16:31 ` Ilya Leoshkevich
2022-12-13 16:35 ` [PATCH v4 00/27] tcg/s390x: misc patches Ilya Leoshkevich
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