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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr Date: Thu, 15 Dec 2022 19:32:44 +0000 Message-ID: <20221215193245.48314-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221215193245.48314-1-ayan.kumar.halder@amd.com> References: <20221215193245.48314-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT085:EE_|MW4PR12MB6973:EE_ X-MS-Office365-Filtering-Correlation-Id: a056e9f1-c7dc-48d5-0034-08daded33581 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S0mUW6MG+5wZbROgtqtvMYcKi+zTiyjkojlyJ0rky6Ua4nxIR33VzC/uktuWMYPCrX+O0nLOaRxdLzAwrzTkpQwPedLkGfUMW9Wd+W7w19IdE+DwPGPsI+ndQzrArU+A2yzLyReTveDba6pwSpDg3piNEsNNeoPwFwbdWAtqvNkP9KnCl+QR+bDr3x54Bi0GwbX75K2fU19icj8+1hCx6sqoi0TyGhbTjaliUSbt2yiS1Yf7qn04MLcjl1AQxg0/qhP7UTL3IH0r/gHGsNfRuvOqbme8ZpCwm+TYVBH08gMM+O9TccXKh8mVgDWETONuh8f4PIoXXR8VKoKAINbaQUI6d6gtnCcWLR3UH6jHzXvBiG535Z41WwLgRrJcfDUs4APONOLN4R29IfWJsiS5sKR62fIn1CR401UqplT1hM61nWBVrOYo2XEPorMl8r1tKzt3dAVSNJ/I5rQ1PpqOWt28YvEHnndStkoyybAAEvjA0Fyjggg3Ql5z067nuLSSUQqCx7LxyAhsuzoJwr2LPX544XrZE3AmXqtj5L//WutNPZnnDv53wkPjATXNBV8kTtTtqNdAtYRM3FxfpzZNNIkQke/2r4GgCprNvX6icmZS8TucPEoelfndb4vSgO6JTaWRD0mnPg1IkHlIIqpPqJyR2NURyBWJUY224s0rmj0sxl+HEMAcxUcRWyug7Qs+Jt7IsXKFOsp0IKxH7PKEhiZTFW9z2k8ucdzihOLQDT4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:CA;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199015)(40470700004)(36840700001)(46966006)(40460700003)(81166007)(356005)(36756003)(82740400003)(40480700001)(86362001)(103116003)(82310400005)(6666004)(316002)(70586007)(478600001)(186003)(26005)(2616005)(6916009)(54906003)(36860700001)(2906002)(47076005)(41300700001)(336012)(70206006)(4326008)(8676002)(8936002)(1076003)(5660300002)(426003)(83380400001)(36900700001);DIR:OUT;SFP:1101; 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Supersections are supported only for paddr greater than 32 bits. 2. Use 0 wherever physical addresses are right shifted for 32 bits. 3. Use PRIx64 to print u64 Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/guest_walk.c | 2 ++ xen/arch/arm/mm.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..4384068285 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -149,6 +149,7 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SECTION_SHIFT) - 1; *ipa = ((paddr_t)pte.sec.base << L1DESC_SECTION_SHIFT) | (gva & mask); } +#ifndef CONFIG_ARM_PA_32 else /* Supersection */ { mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; @@ -157,6 +158,7 @@ static bool guest_walk_sd(const struct vcpu *v, *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; } +#endif /* Set permissions so that the caller can check the flags by herself. */ if ( !pte.sec.ro ) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index be939fb106..3bc9894008 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -229,7 +229,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, pte = mapping[offsets[level]]; - printk("%s[0x%03x] = 0x%"PRIpaddr"\n", + printk("%s[0x%03x] = 0x%"PRIx64"\n", level_strs[level], offsets[level], pte.bits); if ( level == 3 || !pte.walk.valid || !pte.walk.table ) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 5ae180a4cc..522a478ccf 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1184,7 +1184,12 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) reg = (p2maddr & ((1ULL << 32) - 1)); writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); + +#ifndef CONFIG_ARM_PA_32 reg = (p2maddr >> 32); +#else + reg = 0; +#endif if (stage1) reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); -- 2.17.1