[PATCH v2 00/10] riscv: opensbi boot test and cleanups

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Hi,

In this new version I rebased the patches on top of

"[PATCH 00/12] hw/riscv: Improve Spike HTIF emulation fidelity"

from Bin Meng. Patches 4 and 5 from v1 got removed since Bin picked
them in the HTIF changes.

I also removed patches 13, 14 and 15 because I have another cleanup
already planned for the create_fdt() functions and these 3 patches are
more suitable there.

The actual change made from v1 was on patch 1, where I added a riscv32
spike test that is being skipped. The idea is that the skipped test will
be a reminder that we already have a spike riscv32 test that can be
reenabled as soon as the Opensib ROM has the appropriate fix:

 (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: SKIP: requires OpenSBI fix to work


Patch without reviews: 1

Changes from v1:
- patches were rebased with [1]
- patches 13-15: removed
  * will be re-sent in a follow-up series
- patches 4-5: removed since they're picked by Bin in [1]
- patch 1:
  - added a 'skip' riscv32 spike test


Based-on: <20221227064812.1903326-1-bmeng@tinylab.org>

[1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159


Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>

Daniel Henrique Barboza (10):
  tests/avocado: add RISC-V opensbi boot test
  hw/riscv/spike: use 'fdt' from MachineState
  hw/riscv/sifive_u: use 'fdt' from MachineState
  hw/riscv/spike.c: load initrd right after riscv_load_kernel()
  hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
  hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
  hw/riscv/boot.c: use MachineState in riscv_load_initrd()
  hw/riscv/boot.c: use MachineState in riscv_load_kernel()
  hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
  hw/riscv/boot.c: make riscv_load_initrd() static

 hw/riscv/boot.c                | 84 ++++++++++++++++++++++------------
 hw/riscv/microchip_pfsoc.c     | 19 +-------
 hw/riscv/opentitan.c           |  3 +-
 hw/riscv/sifive_e.c            |  3 +-
 hw/riscv/sifive_u.c            | 31 ++-----------
 hw/riscv/spike.c               | 35 ++++----------
 hw/riscv/virt.c                | 20 +-------
 include/hw/riscv/boot.h        |  4 +-
 include/hw/riscv/sifive_u.h    |  3 --
 include/hw/riscv/spike.h       |  2 -
 tests/avocado/riscv_opensbi.py | 77 +++++++++++++++++++++++++++++++
 11 files changed, 149 insertions(+), 132 deletions(-)
 create mode 100644 tests/avocado/riscv_opensbi.py

-- 
2.38.1