From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB76EC54EBC for ; Sat, 7 Jan 2023 11:40:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230178AbjAGLjo (ORCPT ); Sat, 7 Jan 2023 06:39:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232210AbjAGLj1 (ORCPT ); Sat, 7 Jan 2023 06:39:27 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8234E7CBE4; Sat, 7 Jan 2023 03:39:25 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id F399DB81F84; Sat, 7 Jan 2023 11:39:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59644C433F0; Sat, 7 Jan 2023 11:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673091562; bh=6HoEXLmi0SIvQSMUD8M//Ht86bsYFsFai3rcXU0xHLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FXhYAl5KOeXEaAUhWbw9FCEoMdTzoPQ3IjFKVJ8R0Oyu+PpXH/UvCfXU//JBK82XD w+r5WUW6cPJ7F8/D0rCtbVDYhZar0Sy6QP2dKylUJAC7CWBlo1h2yrhnDVDkZqEyUe 5B1tzjsJBu45ZTI/12Af1ACz8+Ins6qA3GYtyRbnKiuvoVp1OrMpST1Dr/WA4dqpCB ZcEzc0DnRs3TDLO4BSu4GK4OLmGi9zXoM0sKOQxlriu9JTVJ+KOxjT9blGHe7YV3As 9EsMfbnx5PJyJP+NvRPgLEtDHycBZUsQcc3BNobK+D0PhE0ItMWQe3tm7Saq12bUmq 7HbUw8u9QoTTA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, ben@decadent.org.uk, bjorn@kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Yipeng Zou Subject: [PATCH -next V13 4/7] riscv: entry: Convert to generic entry Date: Sat, 7 Jan 2023 06:38:35 -0500 Message-Id: <20230107113838.3969149-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230107113838.3969149-1-guoren@kernel.org> References: <20230107113838.3969149-1-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Guo Ren This patch converts riscv to use the generic entry infrastructure from kernel/entry/*. The generic entry makes maintainers' work easier and codes more elegant. Here are the changes: - More clear entry.S with handle_exception and ret_from_exception - Get rid of complex custom signal implementation - Move syscall procedure from assembly to C, which is much more readable. - Connect ret_from_fork & ret_from_kernel_thread to generic entry. - Wrap with irqentry_enter/exit and syscall_enter/exit_from_user_mode - Use the standard preemption code instead of custom Suggested-by: Huacai Chen Reviewed-by: Björn Töpel Tested-by: Yipeng Zou Tested-by: Jisheng Zhang Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Ben Hutchings --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 - arch/riscv/include/asm/entry-common.h | 10 ++ arch/riscv/include/asm/ptrace.h | 10 +- arch/riscv/include/asm/stacktrace.h | 5 + arch/riscv/include/asm/syscall.h | 29 +++ arch/riscv/include/asm/thread_info.h | 13 +- arch/riscv/kernel/entry.S | 242 ++++---------------------- arch/riscv/kernel/ptrace.c | 43 ----- arch/riscv/kernel/signal.c | 28 +-- arch/riscv/kernel/traps.c | 131 ++++++++++++-- arch/riscv/mm/fault.c | 5 +- 12 files changed, 204 insertions(+), 314 deletions(-) create mode 100644 arch/riscv/include/asm/entry-common.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e2b656043abf..552d7fd68aeb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -58,6 +58,7 @@ config RISCV select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_EARLY_IOREMAP + select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP if MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 0e571f6483d9..7c2b8cdb7b77 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -40,7 +40,6 @@ #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ -#define SR_UXL_SHIFT 32 #endif /* SATP flags */ diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h new file mode 100644 index 000000000000..994ed48e8eb8 --- /dev/null +++ b/arch/riscv/include/asm/entry-common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_ENTRY_COMMON_H +#define _ASM_RISCV_ENTRY_COMMON_H + +#include + +extern void handle_page_fault(struct pt_regs *regs); + +#endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index 6ecd461129d2..b5b0adcc85c1 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -53,6 +53,9 @@ struct pt_regs { unsigned long orig_a0; }; +#define PTRACE_SYSEMU 0x1f +#define PTRACE_SYSEMU_SINGLESTEP 0x20 + #ifdef CONFIG_64BIT #define REG_FMT "%016lx" #else @@ -121,8 +124,6 @@ extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, unsigned long frame_pointer); -int do_syscall_trace_enter(struct pt_regs *regs); -void do_syscall_trace_exit(struct pt_regs *regs); /** * regs_get_register() - get register value from its offset @@ -172,6 +173,11 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, return 0; } +static inline int regs_irqs_disabled(struct pt_regs *regs) +{ + return !(regs->status & SR_PIE); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/include/asm/stacktrace.h b/arch/riscv/include/asm/stacktrace.h index 3450c1912afd..f7e8ef2418b9 100644 --- a/arch/riscv/include/asm/stacktrace.h +++ b/arch/riscv/include/asm/stacktrace.h @@ -16,4 +16,9 @@ extern void notrace walk_stackframe(struct task_struct *task, struct pt_regs *re extern void dump_backtrace(struct pt_regs *regs, struct task_struct *task, const char *loglvl); +static inline bool on_thread_stack(void) +{ + return !(((unsigned long)(current->stack) ^ current_stack_pointer) & ~(THREAD_SIZE - 1)); +} + #endif /* _ASM_RISCV_STACKTRACE_H */ diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h index 384a63b86420..8e1e530bb536 100644 --- a/arch/riscv/include/asm/syscall.h +++ b/arch/riscv/include/asm/syscall.h @@ -74,5 +74,34 @@ static inline int syscall_get_arch(struct task_struct *task) #endif } +typedef long (*syscall_t)(ulong, ulong, ulong, ulong, ulong, ulong, ulong); +static inline void syscall_handler(struct pt_regs *regs, ulong syscall) +{ + syscall_t fn; + + regs->epc += 4; + regs->orig_a0 = regs->a0; + + if (syscall >= NR_syscalls) { + regs->a0 = -ENOSYS; + return; + } + +#ifdef CONFIG_COMPAT + if ((regs->status & SR_UXL) == SR_UXL_32) + fn = compat_sys_call_table[syscall]; + else +#endif + fn = sys_call_table[syscall]; + + regs->a0 = fn(regs->orig_a0, regs->a1, regs->a2, + regs->a3, regs->a4, regs->a5, regs->a6); +} + +static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs) +{ + return false; +} + asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t); #endif /* _ASM_RISCV_SYSCALL_H */ diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index 67322f878e0d..7de4fb96f0b5 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -66,6 +66,7 @@ struct thread_info { long kernel_sp; /* Kernel stack pointer */ long user_sp; /* User stack pointer */ int cpu; + unsigned long syscall_work; /* SYSCALL_WORK_ flags */ }; /* @@ -88,26 +89,18 @@ struct thread_info { * - pending work-to-be-done flags are in lowest half-word * - other flags in upper half-word(s) */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_NOTIFY_RESUME 1 /* callback before returning to user */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ #define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */ #define TIF_MEMDIE 5 /* is terminating due to OOM killer */ -#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ -#define TIF_SYSCALL_AUDIT 7 /* syscall auditing */ -#define TIF_SECCOMP 8 /* syscall secure computing */ #define TIF_NOTIFY_SIGNAL 9 /* signal notifications exist */ #define TIF_UPROBE 10 /* uprobe breakpoint or singlestep */ #define TIF_32BIT 11 /* compat-mode 32bit process */ -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) -#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) -#define _TIF_SECCOMP (1 << TIF_SECCOMP) #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) #define _TIF_UPROBE (1 << TIF_UPROBE) @@ -115,8 +108,4 @@ struct thread_info { (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | \ _TIF_NOTIFY_SIGNAL | _TIF_UPROBE) -#define _TIF_SYSCALL_WORK \ - (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT | \ - _TIF_SECCOMP) - #endif /* _ASM_RISCV_THREAD_INFO_H */ diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 99d38fdf8b18..bc322f92ba34 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -14,11 +14,7 @@ #include #include -#if !IS_ENABLED(CONFIG_PREEMPTION) -.set resume_kernel, restore_all -#endif - -ENTRY(handle_exception) +SYM_CODE_START(handle_exception) /* * If coming from userspace, preserve the user thread pointer and load * the kernel thread pointer. If we came from the kernel, the scratch @@ -106,19 +102,8 @@ _save_context: .option norelax la gp, __global_pointer$ .option pop - -#ifdef CONFIG_TRACE_IRQFLAGS - call __trace_hardirqs_off -#endif - -#ifdef CONFIG_CONTEXT_TRACKING_USER - /* If previous state is in user mode, call user_exit_callable(). */ - li a0, SR_PP - and a0, s1, a0 - bnez a0, skip_context_tracking - call user_exit_callable -skip_context_tracking: -#endif + move a0, sp /* pt_regs */ + la ra, ret_from_exception /* * MSB of cause differentiates between @@ -126,38 +111,13 @@ skip_context_tracking: */ bge s4, zero, 1f - la ra, ret_from_exception - /* Handle interrupts */ - move a0, sp /* pt_regs */ - la a1, generic_handle_arch_irq - jr a1 -1: - /* - * Exceptions run with interrupts enabled or disabled depending on the - * state of SR_PIE in m/sstatus. - */ - andi t0, s1, SR_PIE - beqz t0, 1f - /* kprobes, entered via ebreak, must have interrupts disabled. */ - li t0, EXC_BREAKPOINT - beq s4, t0, 1f -#ifdef CONFIG_TRACE_IRQFLAGS - call __trace_hardirqs_on -#endif - csrs CSR_STATUS, SR_IE - + tail do_irq 1: - la ra, ret_from_exception - /* Handle syscalls */ - li t0, EXC_SYSCALL - beq s4, t0, handle_syscall - /* Handle other exceptions */ slli t0, s4, RISCV_LGPTR la t1, excp_vect_table la t2, excp_vect_table_end - move a0, sp /* pt_regs */ add t0, t1, t0 /* Check if exception code lies within bounds */ bgeu t0, t2, 1f @@ -165,95 +125,17 @@ skip_context_tracking: jr t0 1: tail do_trap_unknown +SYM_CODE_END(handle_exception) -handle_syscall: -#ifdef CONFIG_RISCV_M_MODE - /* - * When running is M-Mode (no MMU config), MPIE does not get set. - * As a result, we need to force enable interrupts here because - * handle_exception did not do set SR_IE as it always sees SR_PIE - * being cleared. - */ - csrs CSR_STATUS, SR_IE -#endif -#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING_USER) - /* Recover a0 - a7 for system calls */ - REG_L a0, PT_A0(sp) - REG_L a1, PT_A1(sp) - REG_L a2, PT_A2(sp) - REG_L a3, PT_A3(sp) - REG_L a4, PT_A4(sp) - REG_L a5, PT_A5(sp) - REG_L a6, PT_A6(sp) - REG_L a7, PT_A7(sp) -#endif - /* save the initial A0 value (needed in signal handlers) */ - REG_S a0, PT_ORIG_A0(sp) - /* - * Advance SEPC to avoid executing the original - * scall instruction on sret - */ - addi s2, s2, 0x4 - REG_S s2, PT_EPC(sp) - /* Trace syscalls, but only if requested by the user. */ - REG_L t0, TASK_TI_FLAGS(tp) - andi t0, t0, _TIF_SYSCALL_WORK - bnez t0, handle_syscall_trace_enter -check_syscall_nr: - /* Check to make sure we don't jump to a bogus syscall number. */ - li t0, __NR_syscalls - la s0, sys_ni_syscall - /* - * Syscall number held in a7. - * If syscall number is above allowed value, redirect to ni_syscall. - */ - bgeu a7, t0, 3f -#ifdef CONFIG_COMPAT - REG_L s0, PT_STATUS(sp) - srli s0, s0, SR_UXL_SHIFT - andi s0, s0, (SR_UXL >> SR_UXL_SHIFT) - li t0, (SR_UXL_32 >> SR_UXL_SHIFT) - sub t0, s0, t0 - bnez t0, 1f - - /* Call compat_syscall */ - la s0, compat_sys_call_table - j 2f -1: -#endif - /* Call syscall */ - la s0, sys_call_table -2: - slli t0, a7, RISCV_LGPTR - add s0, s0, t0 - REG_L s0, 0(s0) -3: - jalr s0 - -ret_from_syscall: - /* Set user a0 to kernel a0 */ - REG_S a0, PT_A0(sp) - /* - * We didn't execute the actual syscall. - * Seccomp already set return value for the current task pt_regs. - * (If it was configured with SECCOMP_RET_ERRNO/TRACE) - */ -ret_from_syscall_rejected: -#ifdef CONFIG_DEBUG_RSEQ - move a0, sp - call rseq_syscall -#endif - /* Trace syscalls, but only if requested by the user. */ - REG_L t0, TASK_TI_FLAGS(tp) - andi t0, t0, _TIF_SYSCALL_WORK - bnez t0, handle_syscall_trace_exit - +/* + * The ret_from_exception must be called with interrupt disabled. Here is the + * caller list: + * - handle_exception + * - ret_from_fork + * - ret_from_kernel_thread + */ SYM_CODE_START_NOALIGN(ret_from_exception) REG_L s0, PT_STATUS(sp) - csrc CSR_STATUS, SR_IE -#ifdef CONFIG_TRACE_IRQFLAGS - call __trace_hardirqs_off -#endif #ifdef CONFIG_RISCV_M_MODE /* the MPP value is too large to be used as an immediate arg for addi */ li t0, SR_MPP @@ -261,17 +143,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception) #else andi s0, s0, SR_SPP #endif - bnez s0, resume_kernel -SYM_CODE_END(ret_from_exception) - - /* Interrupts must be disabled here so flags are checked atomically */ - REG_L s0, TASK_TI_FLAGS(tp) /* current_thread_info->flags */ - andi s1, s0, _TIF_WORK_MASK - bnez s1, resume_userspace_slow -resume_userspace: -#ifdef CONFIG_CONTEXT_TRACKING_USER - call user_enter_callable -#endif + bnez s0, 1f /* Save unwound kernel stack pointer in thread_info */ addi s0, sp, PT_SIZE_ON_STACK @@ -282,18 +154,7 @@ resume_userspace: * structures again. */ csrw CSR_SCRATCH, tp - -restore_all: -#ifdef CONFIG_TRACE_IRQFLAGS - REG_L s1, PT_STATUS(sp) - andi t0, s1, SR_PIE - beqz t0, 1f - call __trace_hardirqs_on - j 2f 1: - call __trace_hardirqs_off -2: -#endif REG_L a0, PT_STATUS(sp) /* * The current load reservation is effectively part of the processor's @@ -356,47 +217,10 @@ restore_all: #else sret #endif - -#if IS_ENABLED(CONFIG_PREEMPTION) -resume_kernel: - REG_L s0, TASK_TI_PREEMPT_COUNT(tp) - bnez s0, restore_all - REG_L s0, TASK_TI_FLAGS(tp) - andi s0, s0, _TIF_NEED_RESCHED - beqz s0, restore_all - call preempt_schedule_irq - j restore_all -#endif - -resume_userspace_slow: - /* Enter slow path for supplementary processing */ - move a0, sp /* pt_regs */ - move a1, s0 /* current_thread_info->flags */ - call do_work_pending - j resume_userspace - -/* Slow paths for ptrace. */ -handle_syscall_trace_enter: - move a0, sp - call do_syscall_trace_enter - move t0, a0 - REG_L a0, PT_A0(sp) - REG_L a1, PT_A1(sp) - REG_L a2, PT_A2(sp) - REG_L a3, PT_A3(sp) - REG_L a4, PT_A4(sp) - REG_L a5, PT_A5(sp) - REG_L a6, PT_A6(sp) - REG_L a7, PT_A7(sp) - bnez t0, ret_from_syscall_rejected - j check_syscall_nr -handle_syscall_trace_exit: - move a0, sp - call do_syscall_trace_exit - j ret_from_exception +SYM_CODE_END(ret_from_exception) #ifdef CONFIG_VMAP_STACK -handle_kernel_stack_overflow: +SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) /* * Takes the psuedo-spinlock for the shadow stack, in case multiple * harts are concurrently overflowing their kernel stacks. We could @@ -505,23 +329,25 @@ restore_caller_reg: REG_S s5, PT_TP(sp) move a0, sp tail handle_bad_stack +SYM_CODE_END(handle_kernel_stack_overflow) #endif -END(handle_exception) - -ENTRY(ret_from_fork) +SYM_CODE_START(ret_from_fork) + call schedule_tail + move a0, sp /* pt_regs */ la ra, ret_from_exception - tail schedule_tail -ENDPROC(ret_from_fork) + tail syscall_exit_to_user_mode +SYM_CODE_END(ret_from_fork) -ENTRY(ret_from_kernel_thread) +SYM_CODE_START(ret_from_kernel_thread) call schedule_tail /* Call fn(arg) */ - la ra, ret_from_exception move a0, s1 - jr s0 -ENDPROC(ret_from_kernel_thread) - + jalr s0 + move a0, sp /* pt_regs */ + la ra, ret_from_exception + tail syscall_exit_to_user_mode +SYM_CODE_END(ret_from_kernel_thread) /* * Integer register context switch @@ -533,7 +359,7 @@ ENDPROC(ret_from_kernel_thread) * The value of a0 and a1 must be preserved by this function, as that's how * arguments are passed to schedule_tail. */ -ENTRY(__switch_to) +SYM_FUNC_START(__switch_to) /* Save context into prev->thread */ li a4, TASK_THREAD_RA add a3, a0, a4 @@ -570,7 +396,7 @@ ENTRY(__switch_to) /* The offset of thread_info in task_struct is zero. */ move tp, a1 ret -ENDPROC(__switch_to) +SYM_FUNC_END(__switch_to) #ifndef CONFIG_MMU #define do_page_fault do_trap_unknown @@ -579,7 +405,7 @@ ENDPROC(__switch_to) .section ".rodata" .align LGREG /* Exception vector table */ -ENTRY(excp_vect_table) +SYM_CODE_START(excp_vect_table) RISCV_PTR do_trap_insn_misaligned ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault) RISCV_PTR do_trap_insn_illegal @@ -588,7 +414,7 @@ ENTRY(excp_vect_table) RISCV_PTR do_trap_load_fault RISCV_PTR do_trap_store_misaligned RISCV_PTR do_trap_store_fault - RISCV_PTR do_trap_ecall_u /* system call, gets intercepted */ + RISCV_PTR do_trap_ecall_u /* system call */ RISCV_PTR do_trap_ecall_s RISCV_PTR do_trap_unknown RISCV_PTR do_trap_ecall_m @@ -598,11 +424,11 @@ ENTRY(excp_vect_table) RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ excp_vect_table_end: -END(excp_vect_table) +SYM_CODE_END(excp_vect_table) #ifndef CONFIG_MMU -ENTRY(__user_rt_sigreturn) +SYM_CODE_START(__user_rt_sigreturn) li a7, __NR_rt_sigreturn scall -END(__user_rt_sigreturn) +SYM_CODE_END(__user_rt_sigreturn) #endif diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 44f4b1ca315d..23c48b14a0e7 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,9 +19,6 @@ #include #include -#define CREATE_TRACE_POINTS -#include - enum riscv_regset { REGSET_X, #ifdef CONFIG_FPU @@ -228,46 +225,6 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } -/* - * Allows PTRACE_SYSCALL to work. These are called from entry.S in - * {handle,ret_from}_syscall. - */ -__visible int do_syscall_trace_enter(struct pt_regs *regs) -{ - if (test_thread_flag(TIF_SYSCALL_TRACE)) - if (ptrace_report_syscall_entry(regs)) - return -1; - - /* - * Do the secure computing after ptrace; failures should be fast. - * If this fails we might have return value in a0 from seccomp - * (via SECCOMP_RET_ERRNO/TRACE). - */ - if (secure_computing() == -1) - return -1; - -#ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS - if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) - trace_sys_enter(regs, syscall_get_nr(current, regs)); -#endif - - audit_syscall_entry(regs->a7, regs->a0, regs->a1, regs->a2, regs->a3); - return 0; -} - -__visible void do_syscall_trace_exit(struct pt_regs *regs) -{ - audit_syscall_exit(regs); - - if (test_thread_flag(TIF_SYSCALL_TRACE)) - ptrace_report_syscall_exit(regs, 0); - -#ifdef CONFIG_HAVE_SYSCALL_TRACEPOINTS - if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) - trace_sys_exit(regs, regs_return_value(regs)); -#endif -} - #ifdef CONFIG_COMPAT static int compat_riscv_gpr_get(struct task_struct *target, const struct user_regset *regset, diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index bfb2afa4135f..a7b6bd0df497 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -274,7 +274,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) signal_setup_done(ret, ksig, 0); } -static void do_signal(struct pt_regs *regs) +void arch_do_signal_or_restart(struct pt_regs *regs) { struct ksignal ksig; @@ -311,29 +311,3 @@ static void do_signal(struct pt_regs *regs) */ restore_saved_sigmask(); } - -/* - * Handle any pending work on the resume-to-userspace path, as indicated by - * _TIF_WORK_MASK. Entered from assembly with IRQs off. - */ -asmlinkage __visible void do_work_pending(struct pt_regs *regs, - unsigned long thread_info_flags) -{ - do { - if (thread_info_flags & _TIF_NEED_RESCHED) { - schedule(); - } else { - local_irq_enable(); - if (thread_info_flags & _TIF_UPROBE) - uprobe_notify_resume(regs); - /* Handle pending signal delivery */ - if (thread_info_flags & (_TIF_SIGPENDING | - _TIF_NOTIFY_SIGNAL)) - do_signal(regs); - if (thread_info_flags & _TIF_NOTIFY_RESUME) - resume_user_mode_work(regs); - } - local_irq_disable(); - thread_info_flags = read_thread_flags(); - } while (thread_info_flags & _TIF_WORK_MASK); -} diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 96ec76c54ff2..30855acac850 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -17,12 +17,14 @@ #include #include #include +#include #include #include #include #include #include +#include #include int show_unhandled_signals = 1; @@ -99,10 +101,18 @@ static void do_trap_error(struct pt_regs *regs, int signo, int code, #else #define __trap_section noinstr #endif -#define DO_ERROR_INFO(name, signo, code, str) \ -asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ -{ \ - do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \ +#define DO_ERROR_INFO(name, signo, code, str) \ +asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ +{ \ + if (user_mode(regs)) { \ + irqentry_enter_from_user_mode(regs); \ + do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \ + irqentry_exit_to_user_mode(regs); \ + } else { \ + irqentry_state_t state = irqentry_nmi_enter(regs); \ + do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \ + irqentry_nmi_exit(regs, state); \ + } \ } DO_ERROR_INFO(do_trap_unknown, @@ -124,26 +134,50 @@ DO_ERROR_INFO(do_trap_store_misaligned, int handle_misaligned_load(struct pt_regs *regs); int handle_misaligned_store(struct pt_regs *regs); -asmlinkage void __trap_section do_trap_load_misaligned(struct pt_regs *regs) +asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { - if (!handle_misaligned_load(regs)) - return; - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - load address misaligned"); + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + if (handle_misaligned_load(regs)) + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, + "Oops - load address misaligned"); + + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state = irqentry_nmi_enter(regs); + + if (handle_misaligned_load(regs)) + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, + "Oops - load address misaligned"); + + irqentry_nmi_exit(regs, state); + } } -asmlinkage void __trap_section do_trap_store_misaligned(struct pt_regs *regs) +asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs) { - if (!handle_misaligned_store(regs)) - return; - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, - "Oops - store (or AMO) address misaligned"); + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + if (handle_misaligned_store(regs)) + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, + "Oops - store (or AMO) address misaligned"); + + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state = irqentry_nmi_enter(regs); + + if (handle_misaligned_store(regs)) + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc, + "Oops - store (or AMO) address misaligned"); + + irqentry_nmi_exit(regs, state); + } } #endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); -DO_ERROR_INFO(do_trap_ecall_u, - SIGILL, ILL_ILLTRP, "environment call from U-mode"); DO_ERROR_INFO(do_trap_ecall_s, SIGILL, ILL_ILLTRP, "environment call from S-mode"); DO_ERROR_INFO(do_trap_ecall_m, @@ -159,7 +193,7 @@ static inline unsigned long get_break_insn_length(unsigned long pc) return GET_INSN_LENGTH(insn); } -asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) +void handle_break(struct pt_regs *regs) { #ifdef CONFIG_KPROBES if (kprobe_single_step_handler(regs)) @@ -189,7 +223,68 @@ asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) else die(regs, "Kernel BUG"); } -NOKPROBE_SYMBOL(do_trap_break); + +asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + handle_break(regs); + + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state = irqentry_nmi_enter(regs); + + handle_break(regs); + + irqentry_nmi_exit(regs, state); + } +} + +asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs) +{ + if (user_mode(regs)) { + long syscall = regs->a7; + syscall = syscall_enter_from_user_mode(regs, syscall); + + syscall_handler(regs, (ulong)syscall); + + syscall_exit_to_user_mode(regs); + } else { + irqentry_state_t state = irqentry_nmi_enter(regs); + + do_trap_error(regs, SIGILL, ILL_ILLTRP, regs->epc, + "Oops - environment call from U-mode"); + + irqentry_nmi_exit(regs, state); + } + +} + +asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) +{ + irqentry_state_t state = irqentry_enter(regs); + + handle_page_fault(regs); + + local_irq_disable(); + + irqentry_exit(regs, state); +} + +asmlinkage __visible noinstr void do_irq(struct pt_regs *regs) +{ + struct pt_regs *old_regs; + irqentry_state_t state = irqentry_enter(regs); + + irq_enter_rcu(); + old_regs = set_irq_regs(regs); + handle_arch_irq(regs); + set_irq_regs(old_regs); + irq_exit_rcu(); + + irqentry_exit(regs, state); +} #ifdef CONFIG_GENERIC_BUG int is_valid_bugaddr(unsigned long pc) diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index d86f7cebd4a7..e04593c6cfe3 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -204,7 +204,7 @@ static inline bool access_error(unsigned long cause, struct vm_area_struct *vma) * This routine handles page faults. It determines the address and the * problem, and then passes it off to one of the appropriate routines. */ -asmlinkage void do_page_fault(struct pt_regs *regs) +void handle_page_fault(struct pt_regs *regs) { struct task_struct *tsk; struct vm_area_struct *vma; @@ -251,7 +251,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs) } #endif /* Enable interrupts if they were enabled in the parent context. */ - if (likely(regs->status & SR_PIE)) + if (!regs_irqs_disabled(regs)) local_irq_enable(); /* @@ -351,4 +351,3 @@ asmlinkage void do_page_fault(struct pt_regs *regs) } return; } -NOKPROBE_SYMBOL(do_page_fault); -- 2.36.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22B6AC54EBC for ; Sat, 7 Jan 2023 11:39:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nRUzsr08/1fh7YvK7OapDO+ucdBBKPUEpoqGS3nLST4=; b=tbTLuH/c+yhuoZ QFpDLlTGKt5D1SRYPbUJxIwYclGZUlbbCWmkg+/DJxD9vARBlhIgkmP/YS0f88PQ+LhcqR77O2bHl BnSxYa0NqN5wkdTUfF9W95/W2Ovl+9cTF6f7Cgy7QW1uJuVqw75d21dhKm2bnwVsSL2ury1PjG4Ty W+i5vR4neGNuoFH4RWTpRES87Y+FA1kynQ9+GES/zsHQYpwh49a6ZzlyU3OfgiOLIaI3ZhOy8tWGq SSeC0eTbYc/kZZ058Rq4nYRjNvtatOLhhUPYgXdYDQIfJr0Uaj8FnttJBLDhlVzOWvMAwX4klRpsg tVuu0yi/hhkQ59UQcN6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pE7Xs-004Vvv-OI; Sat, 07 Jan 2023 11:39:28 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pE7Xn-004VsU-RD for linux-riscv@lists.infradead.org; Sat, 07 Jan 2023 11:39:27 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 39A1560BEF; Sat, 7 Jan 2023 11:39:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59644C433F0; Sat, 7 Jan 2023 11:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673091562; bh=6HoEXLmi0SIvQSMUD8M//Ht86bsYFsFai3rcXU0xHLI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FXhYAl5KOeXEaAUhWbw9FCEoMdTzoPQ3IjFKVJ8R0Oyu+PpXH/UvCfXU//JBK82XD w+r5WUW6cPJ7F8/D0rCtbVDYhZar0Sy6QP2dKylUJAC7CWBlo1h2yrhnDVDkZqEyUe 5B1tzjsJBu45ZTI/12Af1ACz8+Ins6qA3GYtyRbnKiuvoVp1OrMpST1Dr/WA4dqpCB ZcEzc0DnRs3TDLO4BSu4GK4OLmGi9zXoM0sKOQxlriu9JTVJ+KOxjT9blGHe7YV3As 9EsMfbnx5PJyJP+NvRPgLEtDHycBZUsQcc3BNobK+D0PhE0ItMWQe3tm7Saq12bUmq 7HbUw8u9QoTTA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, lazyparser@gmail.com, falcon@tinylab.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, ben@decadent.org.uk, bjorn@kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Yipeng Zou Subject: [PATCH -next V13 4/7] riscv: entry: Convert to generic entry Date: Sat, 7 Jan 2023 06:38:35 -0500 Message-Id: <20230107113838.3969149-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230107113838.3969149-1-guoren@kernel.org> References: <20230107113838.3969149-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230107_033923_989753_066ACE80 X-CRM114-Status: GOOD ( 30.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RnJvbTogR3VvIFJlbiA8Z3VvcmVuQGxpbnV4LmFsaWJhYmEuY29tPgoKVGhpcyBwYXRjaCBjb252 ZXJ0cyByaXNjdiB0byB1c2UgdGhlIGdlbmVyaWMgZW50cnkgaW5mcmFzdHJ1Y3R1cmUgZnJvbQpr ZXJuZWwvZW50cnkvKi4gVGhlIGdlbmVyaWMgZW50cnkgbWFrZXMgbWFpbnRhaW5lcnMnIHdvcmsg ZWFzaWVyIGFuZApjb2RlcyBtb3JlIGVsZWdhbnQuIEhlcmUgYXJlIHRoZSBjaGFuZ2VzOgoKIC0g TW9yZSBjbGVhciBlbnRyeS5TIHdpdGggaGFuZGxlX2V4Y2VwdGlvbiBhbmQgcmV0X2Zyb21fZXhj ZXB0aW9uCiAtIEdldCByaWQgb2YgY29tcGxleCBjdXN0b20gc2lnbmFsIGltcGxlbWVudGF0aW9u CiAtIE1vdmUgc3lzY2FsbCBwcm9jZWR1cmUgZnJvbSBhc3NlbWJseSB0byBDLCB3aGljaCBpcyBt dWNoIG1vcmUKICAgcmVhZGFibGUuCiAtIENvbm5lY3QgcmV0X2Zyb21fZm9yayAmIHJldF9mcm9t X2tlcm5lbF90aHJlYWQgdG8gZ2VuZXJpYyBlbnRyeS4KIC0gV3JhcCB3aXRoIGlycWVudHJ5X2Vu dGVyL2V4aXQgYW5kIHN5c2NhbGxfZW50ZXIvZXhpdF9mcm9tX3VzZXJfbW9kZQogLSBVc2UgdGhl IHN0YW5kYXJkIHByZWVtcHRpb24gY29kZSBpbnN0ZWFkIG9mIGN1c3RvbQoKU3VnZ2VzdGVkLWJ5 OiBIdWFjYWkgQ2hlbiA8Y2hlbmh1YWNhaUBrZXJuZWwub3JnPgpSZXZpZXdlZC1ieTogQmrDtnJu IFTDtnBlbCA8Ympvcm5Acml2b3NpbmMuY29tPgpUZXN0ZWQtYnk6IFlpcGVuZyBab3UgPHpvdXlp cGVuZ0BodWF3ZWkuY29tPgpUZXN0ZWQtYnk6IEppc2hlbmcgWmhhbmcgPGpzemhhbmdAa2VybmVs Lm9yZz4KU2lnbmVkLW9mZi1ieTogR3VvIFJlbiA8Z3VvcmVuQGxpbnV4LmFsaWJhYmEuY29tPgpT aWduZWQtb2ZmLWJ5OiBHdW8gUmVuIDxndW9yZW5Aa2VybmVsLm9yZz4KQ2M6IEJlbiBIdXRjaGlu Z3MgPGJlbkBkZWNhZGVudC5vcmcudWs+Ci0tLQogYXJjaC9yaXNjdi9LY29uZmlnICAgICAgICAg ICAgICAgICAgICB8ICAgMSArCiBhcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2Nzci5oICAgICAgICAg IHwgICAxIC0KIGFyY2gvcmlzY3YvaW5jbHVkZS9hc20vZW50cnktY29tbW9uLmggfCAgMTAgKysK IGFyY2gvcmlzY3YvaW5jbHVkZS9hc20vcHRyYWNlLmggICAgICAgfCAgMTAgKy0KIGFyY2gvcmlz Y3YvaW5jbHVkZS9hc20vc3RhY2t0cmFjZS5oICAgfCAgIDUgKwogYXJjaC9yaXNjdi9pbmNsdWRl L2FzbS9zeXNjYWxsLmggICAgICB8ICAyOSArKysKIGFyY2gvcmlzY3YvaW5jbHVkZS9hc20vdGhy ZWFkX2luZm8uaCAgfCAgMTMgKy0KIGFyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMgICAgICAgICAg ICAgfCAyNDIgKysrKy0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KIGFyY2gvcmlzY3Yva2VybmVsL3B0 cmFjZS5jICAgICAgICAgICAgfCAgNDMgLS0tLS0KIGFyY2gvcmlzY3Yva2VybmVsL3NpZ25hbC5j ICAgICAgICAgICAgfCAgMjggKy0tCiBhcmNoL3Jpc2N2L2tlcm5lbC90cmFwcy5jICAgICAgICAg ICAgIHwgMTMxICsrKysrKysrKysrKy0tCiBhcmNoL3Jpc2N2L21tL2ZhdWx0LmMgICAgICAgICAg ICAgICAgIHwgICA1ICstCiAxMiBmaWxlcyBjaGFuZ2VkLCAyMDQgaW5zZXJ0aW9ucygrKSwgMzE0 IGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvcmlzY3YvaW5jbHVkZS9hc20v ZW50cnktY29tbW9uLmgKCmRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L0tjb25maWcgYi9hcmNoL3Jp c2N2L0tjb25maWcKaW5kZXggZTJiNjU2MDQzYWJmLi41NTJkN2ZkNjhhZWIgMTAwNjQ0Ci0tLSBh L2FyY2gvcmlzY3YvS2NvbmZpZworKysgYi9hcmNoL3Jpc2N2L0tjb25maWcKQEAgLTU4LDYgKzU4 LDcgQEAgY29uZmlnIFJJU0NWCiAJc2VsZWN0IEdFTkVSSUNfQVRPTUlDNjQgaWYgITY0QklUCiAJ c2VsZWN0IEdFTkVSSUNfQ0xPQ0tFVkVOVFNfQlJPQURDQVNUIGlmIFNNUAogCXNlbGVjdCBHRU5F UklDX0VBUkxZX0lPUkVNQVAKKwlzZWxlY3QgR0VORVJJQ19FTlRSWQogCXNlbGVjdCBHRU5FUklD X0dFVFRJTUVPRkRBWSBpZiBIQVZFX0dFTkVSSUNfVkRTTwogCXNlbGVjdCBHRU5FUklDX0lETEVf UE9MTF9TRVRVUAogCXNlbGVjdCBHRU5FUklDX0lPUkVNQVAgaWYgTU1VCmRpZmYgLS1naXQgYS9h cmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2Nzci5oIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9jc3Iu aAppbmRleCAwZTU3MWY2NDgzZDkuLjdjMmI4Y2RiN2I3NyAxMDA2NDQKLS0tIGEvYXJjaC9yaXNj di9pbmNsdWRlL2FzbS9jc3IuaAorKysgYi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2Nzci5oCkBA IC00MCw3ICs0MCw2IEBACiAjZGVmaW5lIFNSX1VYTAkJX0FDKDB4MzAwMDAwMDAwLCBVTCkgLyog WExFTiBtYXNrIGZvciBVLW1vZGUgKi8KICNkZWZpbmUgU1JfVVhMXzMyCV9BQygweDEwMDAwMDAw MCwgVUwpIC8qIFhMRU4gPSAzMiBmb3IgVS1tb2RlICovCiAjZGVmaW5lIFNSX1VYTF82NAlfQUMo MHgyMDAwMDAwMDAsIFVMKSAvKiBYTEVOID0gNjQgZm9yIFUtbW9kZSAqLwotI2RlZmluZSBTUl9V WExfU0hJRlQJMzIKICNlbmRpZgogCiAvKiBTQVRQIGZsYWdzICovCmRpZmYgLS1naXQgYS9hcmNo L3Jpc2N2L2luY2x1ZGUvYXNtL2VudHJ5LWNvbW1vbi5oIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2Fz bS9lbnRyeS1jb21tb24uaApuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAwMDAwMDAwMDAu Ljk5NGVkNDhlOGViOAotLS0gL2Rldi9udWxsCisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20v ZW50cnktY29tbW9uLmgKQEAgLTAsMCArMSwxMCBAQAorLyogU1BEWC1MaWNlbnNlLUlkZW50aWZp ZXI6IEdQTC0yLjAgKi8KKworI2lmbmRlZiBfQVNNX1JJU0NWX0VOVFJZX0NPTU1PTl9ICisjZGVm aW5lIF9BU01fUklTQ1ZfRU5UUllfQ09NTU9OX0gKKworI2luY2x1ZGUgPGFzbS9zdGFja3RyYWNl Lmg+CisKK2V4dGVybiB2b2lkIGhhbmRsZV9wYWdlX2ZhdWx0KHN0cnVjdCBwdF9yZWdzICpyZWdz KTsKKworI2VuZGlmIC8qIF9BU01fUklTQ1ZfRU5UUllfQ09NTU9OX0ggKi8KZGlmZiAtLWdpdCBh L2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vcHRyYWNlLmggYi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNt L3B0cmFjZS5oCmluZGV4IDZlY2Q0NjExMjlkMi4uYjViMGFkY2M4NWMxIDEwMDY0NAotLS0gYS9h cmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3B0cmFjZS5oCisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9h c20vcHRyYWNlLmgKQEAgLTUzLDYgKzUzLDkgQEAgc3RydWN0IHB0X3JlZ3MgewogCXVuc2lnbmVk IGxvbmcgb3JpZ19hMDsKIH07CiAKKyNkZWZpbmUgUFRSQUNFX1NZU0VNVQkJCTB4MWYKKyNkZWZp bmUgUFRSQUNFX1NZU0VNVV9TSU5HTEVTVEVQCTB4MjAKKwogI2lmZGVmIENPTkZJR182NEJJVAog I2RlZmluZSBSRUdfRk1UICIlMDE2bHgiCiAjZWxzZQpAQCAtMTIxLDggKzEyNCw2IEBAIGV4dGVy biB1bnNpZ25lZCBsb25nIHJlZ3NfZ2V0X2tlcm5lbF9zdGFja19udGgoc3RydWN0IHB0X3JlZ3Mg KnJlZ3MsCiAKIHZvaWQgcHJlcGFyZV9mdHJhY2VfcmV0dXJuKHVuc2lnbmVkIGxvbmcgKnBhcmVu dCwgdW5zaWduZWQgbG9uZyBzZWxmX2FkZHIsCiAJCQkgICB1bnNpZ25lZCBsb25nIGZyYW1lX3Bv aW50ZXIpOwotaW50IGRvX3N5c2NhbGxfdHJhY2VfZW50ZXIoc3RydWN0IHB0X3JlZ3MgKnJlZ3Mp Owotdm9pZCBkb19zeXNjYWxsX3RyYWNlX2V4aXQoc3RydWN0IHB0X3JlZ3MgKnJlZ3MpOwogCiAv KioKICAqIHJlZ3NfZ2V0X3JlZ2lzdGVyKCkgLSBnZXQgcmVnaXN0ZXIgdmFsdWUgZnJvbSBpdHMg b2Zmc2V0CkBAIC0xNzIsNiArMTczLDExIEBAIHN0YXRpYyBpbmxpbmUgdW5zaWduZWQgbG9uZyBy ZWdzX2dldF9rZXJuZWxfYXJndW1lbnQoc3RydWN0IHB0X3JlZ3MgKnJlZ3MsCiAJcmV0dXJuIDA7 CiB9CiAKK3N0YXRpYyBpbmxpbmUgaW50IHJlZ3NfaXJxc19kaXNhYmxlZChzdHJ1Y3QgcHRfcmVn cyAqcmVncykKK3sKKwlyZXR1cm4gIShyZWdzLT5zdGF0dXMgJiBTUl9QSUUpOworfQorCiAjZW5k aWYgLyogX19BU1NFTUJMWV9fICovCiAKICNlbmRpZiAvKiBfQVNNX1JJU0NWX1BUUkFDRV9IICov CmRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3N0YWNrdHJhY2UuaCBiL2FyY2gv cmlzY3YvaW5jbHVkZS9hc20vc3RhY2t0cmFjZS5oCmluZGV4IDM0NTBjMTkxMmFmZC4uZjdlOGVm MjQxOGI5IDEwMDY0NAotLS0gYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3N0YWNrdHJhY2UuaAor KysgYi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3N0YWNrdHJhY2UuaApAQCAtMTYsNCArMTYsOSBA QCBleHRlcm4gdm9pZCBub3RyYWNlIHdhbGtfc3RhY2tmcmFtZShzdHJ1Y3QgdGFza19zdHJ1Y3Qg KnRhc2ssIHN0cnVjdCBwdF9yZWdzICpyZQogZXh0ZXJuIHZvaWQgZHVtcF9iYWNrdHJhY2Uoc3Ry dWN0IHB0X3JlZ3MgKnJlZ3MsIHN0cnVjdCB0YXNrX3N0cnVjdCAqdGFzaywKIAkJCSAgIGNvbnN0 IGNoYXIgKmxvZ2x2bCk7CiAKK3N0YXRpYyBpbmxpbmUgYm9vbCBvbl90aHJlYWRfc3RhY2sodm9p ZCkKK3sKKwlyZXR1cm4gISgoKHVuc2lnbmVkIGxvbmcpKGN1cnJlbnQtPnN0YWNrKSBeIGN1cnJl bnRfc3RhY2tfcG9pbnRlcikgJiB+KFRIUkVBRF9TSVpFIC0gMSkpOworfQorCiAjZW5kaWYgLyog X0FTTV9SSVNDVl9TVEFDS1RSQUNFX0ggKi8KZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvaW5jbHVk ZS9hc20vc3lzY2FsbC5oIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9zeXNjYWxsLmgKaW5kZXgg Mzg0YTYzYjg2NDIwLi44ZTFlNTMwYmI1MzYgMTAwNjQ0Ci0tLSBhL2FyY2gvcmlzY3YvaW5jbHVk ZS9hc20vc3lzY2FsbC5oCisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3lzY2FsbC5oCkBA IC03NCw1ICs3NCwzNCBAQCBzdGF0aWMgaW5saW5lIGludCBzeXNjYWxsX2dldF9hcmNoKHN0cnVj dCB0YXNrX3N0cnVjdCAqdGFzaykKICNlbmRpZgogfQogCit0eXBlZGVmIGxvbmcgKCpzeXNjYWxs X3QpKHVsb25nLCB1bG9uZywgdWxvbmcsIHVsb25nLCB1bG9uZywgdWxvbmcsIHVsb25nKTsKK3N0 YXRpYyBpbmxpbmUgdm9pZCBzeXNjYWxsX2hhbmRsZXIoc3RydWN0IHB0X3JlZ3MgKnJlZ3MsIHVs b25nIHN5c2NhbGwpCit7CisJc3lzY2FsbF90IGZuOworCisJcmVncy0+ZXBjICs9IDQ7CisJcmVn cy0+b3JpZ19hMCA9IHJlZ3MtPmEwOworCisJaWYgKHN5c2NhbGwgPj0gTlJfc3lzY2FsbHMpIHsK KwkJcmVncy0+YTAgPSAtRU5PU1lTOworCQlyZXR1cm47CisJfQorCisjaWZkZWYgQ09ORklHX0NP TVBBVAorCWlmICgocmVncy0+c3RhdHVzICYgU1JfVVhMKSA9PSBTUl9VWExfMzIpCisJCWZuID0g Y29tcGF0X3N5c19jYWxsX3RhYmxlW3N5c2NhbGxdOworCWVsc2UKKyNlbmRpZgorCQlmbiA9IHN5 c19jYWxsX3RhYmxlW3N5c2NhbGxdOworCisJcmVncy0+YTAgPSBmbihyZWdzLT5vcmlnX2EwLCBy ZWdzLT5hMSwgcmVncy0+YTIsCisJCSAgICAgIHJlZ3MtPmEzLCByZWdzLT5hNCwgcmVncy0+YTUs IHJlZ3MtPmE2KTsKK30KKworc3RhdGljIGlubGluZSBib29sIGFyY2hfc3lzY2FsbF9pc192ZHNv X3NpZ3JldHVybihzdHJ1Y3QgcHRfcmVncyAqcmVncykKK3sKKwlyZXR1cm4gZmFsc2U7Cit9CisK IGFzbWxpbmthZ2UgbG9uZyBzeXNfcmlzY3ZfZmx1c2hfaWNhY2hlKHVpbnRwdHJfdCwgdWludHB0 cl90LCB1aW50cHRyX3QpOwogI2VuZGlmCS8qIF9BU01fUklTQ1ZfU1lTQ0FMTF9IICovCmRpZmYg LS1naXQgYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3RocmVhZF9pbmZvLmggYi9hcmNoL3Jpc2N2 L2luY2x1ZGUvYXNtL3RocmVhZF9pbmZvLmgKaW5kZXggNjczMjJmODc4ZTBkLi43ZGU0ZmI5NmYw YjUgMTAwNjQ0Ci0tLSBhL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vdGhyZWFkX2luZm8uaAorKysg Yi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3RocmVhZF9pbmZvLmgKQEAgLTY2LDYgKzY2LDcgQEAg c3RydWN0IHRocmVhZF9pbmZvIHsKIAlsb25nCQkJa2VybmVsX3NwOwkvKiBLZXJuZWwgc3RhY2sg cG9pbnRlciAqLwogCWxvbmcJCQl1c2VyX3NwOwkvKiBVc2VyIHN0YWNrIHBvaW50ZXIgKi8KIAlp bnQJCQljcHU7CisJdW5zaWduZWQgbG9uZwkJc3lzY2FsbF93b3JrOwkvKiBTWVNDQUxMX1dPUktf IGZsYWdzICovCiB9OwogCiAvKgpAQCAtODgsMjYgKzg5LDE4IEBAIHN0cnVjdCB0aHJlYWRfaW5m byB7CiAgKiAtIHBlbmRpbmcgd29yay10by1iZS1kb25lIGZsYWdzIGFyZSBpbiBsb3dlc3QgaGFs Zi13b3JkCiAgKiAtIG90aGVyIGZsYWdzIGluIHVwcGVyIGhhbGYtd29yZChzKQogICovCi0jZGVm aW5lIFRJRl9TWVNDQUxMX1RSQUNFCTAJLyogc3lzY2FsbCB0cmFjZSBhY3RpdmUgKi8KICNkZWZp bmUgVElGX05PVElGWV9SRVNVTUUJMQkvKiBjYWxsYmFjayBiZWZvcmUgcmV0dXJuaW5nIHRvIHVz ZXIgKi8KICNkZWZpbmUgVElGX1NJR1BFTkRJTkcJCTIJLyogc2lnbmFsIHBlbmRpbmcgKi8KICNk ZWZpbmUgVElGX05FRURfUkVTQ0hFRAkzCS8qIHJlc2NoZWR1bGluZyBuZWNlc3NhcnkgKi8KICNk ZWZpbmUgVElGX1JFU1RPUkVfU0lHTUFTSwk0CS8qIHJlc3RvcmUgc2lnbmFsIG1hc2sgaW4gZG9f c2lnbmFsKCkgKi8KICNkZWZpbmUgVElGX01FTURJRQkJNQkvKiBpcyB0ZXJtaW5hdGluZyBkdWUg dG8gT09NIGtpbGxlciAqLwotI2RlZmluZSBUSUZfU1lTQ0FMTF9UUkFDRVBPSU5UICA2ICAgICAg IC8qIHN5c2NhbGwgdHJhY2Vwb2ludCBpbnN0cnVtZW50YXRpb24gKi8KLSNkZWZpbmUgVElGX1NZ U0NBTExfQVVESVQJNwkvKiBzeXNjYWxsIGF1ZGl0aW5nICovCi0jZGVmaW5lIFRJRl9TRUNDT01Q CQk4CS8qIHN5c2NhbGwgc2VjdXJlIGNvbXB1dGluZyAqLwogI2RlZmluZSBUSUZfTk9USUZZX1NJ R05BTAk5CS8qIHNpZ25hbCBub3RpZmljYXRpb25zIGV4aXN0ICovCiAjZGVmaW5lIFRJRl9VUFJP QkUJCTEwCS8qIHVwcm9iZSBicmVha3BvaW50IG9yIHNpbmdsZXN0ZXAgKi8KICNkZWZpbmUgVElG XzMyQklUCQkxMQkvKiBjb21wYXQtbW9kZSAzMmJpdCBwcm9jZXNzICovCiAKLSNkZWZpbmUgX1RJ Rl9TWVNDQUxMX1RSQUNFCSgxIDw8IFRJRl9TWVNDQUxMX1RSQUNFKQogI2RlZmluZSBfVElGX05P VElGWV9SRVNVTUUJKDEgPDwgVElGX05PVElGWV9SRVNVTUUpCiAjZGVmaW5lIF9USUZfU0lHUEVO RElORwkJKDEgPDwgVElGX1NJR1BFTkRJTkcpCiAjZGVmaW5lIF9USUZfTkVFRF9SRVNDSEVECSgx IDw8IFRJRl9ORUVEX1JFU0NIRUQpCi0jZGVmaW5lIF9USUZfU1lTQ0FMTF9UUkFDRVBPSU5UCSgx IDw8IFRJRl9TWVNDQUxMX1RSQUNFUE9JTlQpCi0jZGVmaW5lIF9USUZfU1lTQ0FMTF9BVURJVAko MSA8PCBUSUZfU1lTQ0FMTF9BVURJVCkKLSNkZWZpbmUgX1RJRl9TRUNDT01QCQkoMSA8PCBUSUZf U0VDQ09NUCkKICNkZWZpbmUgX1RJRl9OT1RJRllfU0lHTkFMCSgxIDw8IFRJRl9OT1RJRllfU0lH TkFMKQogI2RlZmluZSBfVElGX1VQUk9CRQkJKDEgPDwgVElGX1VQUk9CRSkKIApAQCAtMTE1LDgg KzEwOCw0IEBAIHN0cnVjdCB0aHJlYWRfaW5mbyB7CiAJKF9USUZfTk9USUZZX1JFU1VNRSB8IF9U SUZfU0lHUEVORElORyB8IF9USUZfTkVFRF9SRVNDSEVEIHwgXAogCSBfVElGX05PVElGWV9TSUdO QUwgfCBfVElGX1VQUk9CRSkKIAotI2RlZmluZSBfVElGX1NZU0NBTExfV09SSyBcCi0JKF9USUZf U1lTQ0FMTF9UUkFDRSB8IF9USUZfU1lTQ0FMTF9UUkFDRVBPSU5UIHwgX1RJRl9TWVNDQUxMX0FV RElUIHwgXAotCSBfVElGX1NFQ0NPTVApCi0KICNlbmRpZiAvKiBfQVNNX1JJU0NWX1RIUkVBRF9J TkZPX0ggKi8KZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMgYi9hcmNoL3Jp c2N2L2tlcm5lbC9lbnRyeS5TCmluZGV4IDk5ZDM4ZmRmOGIxOC4uYmMzMjJmOTJiYTM0IDEwMDY0 NAotLS0gYS9hcmNoL3Jpc2N2L2tlcm5lbC9lbnRyeS5TCisrKyBiL2FyY2gvcmlzY3Yva2VybmVs L2VudHJ5LlMKQEAgLTE0LDExICsxNCw3IEBACiAjaW5jbHVkZSA8YXNtL2FzbS1vZmZzZXRzLmg+ CiAjaW5jbHVkZSA8YXNtL2VycmF0YV9saXN0Lmg+CiAKLSNpZiAhSVNfRU5BQkxFRChDT05GSUdf UFJFRU1QVElPTikKLS5zZXQgcmVzdW1lX2tlcm5lbCwgcmVzdG9yZV9hbGwKLSNlbmRpZgotCi1F TlRSWShoYW5kbGVfZXhjZXB0aW9uKQorU1lNX0NPREVfU1RBUlQoaGFuZGxlX2V4Y2VwdGlvbikK IAkvKgogCSAqIElmIGNvbWluZyBmcm9tIHVzZXJzcGFjZSwgcHJlc2VydmUgdGhlIHVzZXIgdGhy ZWFkIHBvaW50ZXIgYW5kIGxvYWQKIAkgKiB0aGUga2VybmVsIHRocmVhZCBwb2ludGVyLiAgSWYg d2UgY2FtZSBmcm9tIHRoZSBrZXJuZWwsIHRoZSBzY3JhdGNoCkBAIC0xMDYsMTkgKzEwMiw4IEBA IF9zYXZlX2NvbnRleHQ6CiAub3B0aW9uIG5vcmVsYXgKIAlsYSBncCwgX19nbG9iYWxfcG9pbnRl ciQKIC5vcHRpb24gcG9wCi0KLSNpZmRlZiBDT05GSUdfVFJBQ0VfSVJRRkxBR1MKLQljYWxsIF9f dHJhY2VfaGFyZGlycXNfb2ZmCi0jZW5kaWYKLQotI2lmZGVmIENPTkZJR19DT05URVhUX1RSQUNL SU5HX1VTRVIKLQkvKiBJZiBwcmV2aW91cyBzdGF0ZSBpcyBpbiB1c2VyIG1vZGUsIGNhbGwgdXNl cl9leGl0X2NhbGxhYmxlKCkuICovCi0JbGkgICBhMCwgU1JfUFAKLQlhbmQgYTAsIHMxLCBhMAot CWJuZXogYTAsIHNraXBfY29udGV4dF90cmFja2luZwotCWNhbGwgdXNlcl9leGl0X2NhbGxhYmxl Ci1za2lwX2NvbnRleHRfdHJhY2tpbmc6Ci0jZW5kaWYKKwltb3ZlIGEwLCBzcCAvKiBwdF9yZWdz ICovCisJbGEgcmEsIHJldF9mcm9tX2V4Y2VwdGlvbgogCiAJLyoKIAkgKiBNU0Igb2YgY2F1c2Ug ZGlmZmVyZW50aWF0ZXMgYmV0d2VlbgpAQCAtMTI2LDM4ICsxMTEsMTMgQEAgc2tpcF9jb250ZXh0 X3RyYWNraW5nOgogCSAqLwogCWJnZSBzNCwgemVybywgMWYKIAotCWxhIHJhLCByZXRfZnJvbV9l eGNlcHRpb24KLQogCS8qIEhhbmRsZSBpbnRlcnJ1cHRzICovCi0JbW92ZSBhMCwgc3AgLyogcHRf cmVncyAqLwotCWxhIGExLCBnZW5lcmljX2hhbmRsZV9hcmNoX2lycQotCWpyIGExCi0xOgotCS8q Ci0JICogRXhjZXB0aW9ucyBydW4gd2l0aCBpbnRlcnJ1cHRzIGVuYWJsZWQgb3IgZGlzYWJsZWQg ZGVwZW5kaW5nIG9uIHRoZQotCSAqIHN0YXRlIG9mIFNSX1BJRSBpbiBtL3NzdGF0dXMuCi0JICov Ci0JYW5kaSB0MCwgczEsIFNSX1BJRQotCWJlcXogdDAsIDFmCi0JLyoga3Byb2JlcywgZW50ZXJl ZCB2aWEgZWJyZWFrLCBtdXN0IGhhdmUgaW50ZXJydXB0cyBkaXNhYmxlZC4gKi8KLQlsaSB0MCwg RVhDX0JSRUFLUE9JTlQKLQliZXEgczQsIHQwLCAxZgotI2lmZGVmIENPTkZJR19UUkFDRV9JUlFG TEFHUwotCWNhbGwgX190cmFjZV9oYXJkaXJxc19vbgotI2VuZGlmCi0JY3NycyBDU1JfU1RBVFVT LCBTUl9JRQotCisJdGFpbCBkb19pcnEKIDE6Ci0JbGEgcmEsIHJldF9mcm9tX2V4Y2VwdGlvbgot CS8qIEhhbmRsZSBzeXNjYWxscyAqLwotCWxpIHQwLCBFWENfU1lTQ0FMTAotCWJlcSBzNCwgdDAs IGhhbmRsZV9zeXNjYWxsCi0KIAkvKiBIYW5kbGUgb3RoZXIgZXhjZXB0aW9ucyAqLwogCXNsbGkg dDAsIHM0LCBSSVNDVl9MR1BUUgogCWxhIHQxLCBleGNwX3ZlY3RfdGFibGUKIAlsYSB0MiwgZXhj cF92ZWN0X3RhYmxlX2VuZAotCW1vdmUgYTAsIHNwIC8qIHB0X3JlZ3MgKi8KIAlhZGQgdDAsIHQx LCB0MAogCS8qIENoZWNrIGlmIGV4Y2VwdGlvbiBjb2RlIGxpZXMgd2l0aGluIGJvdW5kcyAqLwog CWJnZXUgdDAsIHQyLCAxZgpAQCAtMTY1LDk1ICsxMjUsMTcgQEAgc2tpcF9jb250ZXh0X3RyYWNr aW5nOgogCWpyIHQwCiAxOgogCXRhaWwgZG9fdHJhcF91bmtub3duCitTWU1fQ09ERV9FTkQoaGFu ZGxlX2V4Y2VwdGlvbikKIAotaGFuZGxlX3N5c2NhbGw6Ci0jaWZkZWYgQ09ORklHX1JJU0NWX01f TU9ERQotCS8qCi0JICogV2hlbiBydW5uaW5nIGlzIE0tTW9kZSAobm8gTU1VIGNvbmZpZyksIE1Q SUUgZG9lcyBub3QgZ2V0IHNldC4KLQkgKiBBcyBhIHJlc3VsdCwgd2UgbmVlZCB0byBmb3JjZSBl bmFibGUgaW50ZXJydXB0cyBoZXJlIGJlY2F1c2UKLQkgKiBoYW5kbGVfZXhjZXB0aW9uIGRpZCBu b3QgZG8gc2V0IFNSX0lFIGFzIGl0IGFsd2F5cyBzZWVzIFNSX1BJRQotCSAqIGJlaW5nIGNsZWFy ZWQuCi0JICovCi0JY3NycyBDU1JfU1RBVFVTLCBTUl9JRQotI2VuZGlmCi0jaWYgZGVmaW5lZChD T05GSUdfVFJBQ0VfSVJRRkxBR1MpIHx8IGRlZmluZWQoQ09ORklHX0NPTlRFWFRfVFJBQ0tJTkdf VVNFUikKLQkvKiBSZWNvdmVyIGEwIC0gYTcgZm9yIHN5c3RlbSBjYWxscyAqLwotCVJFR19MIGEw LCBQVF9BMChzcCkKLQlSRUdfTCBhMSwgUFRfQTEoc3ApCi0JUkVHX0wgYTIsIFBUX0EyKHNwKQot CVJFR19MIGEzLCBQVF9BMyhzcCkKLQlSRUdfTCBhNCwgUFRfQTQoc3ApCi0JUkVHX0wgYTUsIFBU X0E1KHNwKQotCVJFR19MIGE2LCBQVF9BNihzcCkKLQlSRUdfTCBhNywgUFRfQTcoc3ApCi0jZW5k aWYKLQkgLyogc2F2ZSB0aGUgaW5pdGlhbCBBMCB2YWx1ZSAobmVlZGVkIGluIHNpZ25hbCBoYW5k bGVycykgKi8KLQlSRUdfUyBhMCwgUFRfT1JJR19BMChzcCkKLQkvKgotCSAqIEFkdmFuY2UgU0VQ QyB0byBhdm9pZCBleGVjdXRpbmcgdGhlIG9yaWdpbmFsCi0JICogc2NhbGwgaW5zdHJ1Y3Rpb24g b24gc3JldAotCSAqLwotCWFkZGkgczIsIHMyLCAweDQKLQlSRUdfUyBzMiwgUFRfRVBDKHNwKQot CS8qIFRyYWNlIHN5c2NhbGxzLCBidXQgb25seSBpZiByZXF1ZXN0ZWQgYnkgdGhlIHVzZXIuICov Ci0JUkVHX0wgdDAsIFRBU0tfVElfRkxBR1ModHApCi0JYW5kaSB0MCwgdDAsIF9USUZfU1lTQ0FM TF9XT1JLCi0JYm5leiB0MCwgaGFuZGxlX3N5c2NhbGxfdHJhY2VfZW50ZXIKLWNoZWNrX3N5c2Nh bGxfbnI6Ci0JLyogQ2hlY2sgdG8gbWFrZSBzdXJlIHdlIGRvbid0IGp1bXAgdG8gYSBib2d1cyBz eXNjYWxsIG51bWJlci4gKi8KLQlsaSB0MCwgX19OUl9zeXNjYWxscwotCWxhIHMwLCBzeXNfbmlf c3lzY2FsbAotCS8qCi0JICogU3lzY2FsbCBudW1iZXIgaGVsZCBpbiBhNy4KLQkgKiBJZiBzeXNj YWxsIG51bWJlciBpcyBhYm92ZSBhbGxvd2VkIHZhbHVlLCByZWRpcmVjdCB0byBuaV9zeXNjYWxs LgotCSAqLwotCWJnZXUgYTcsIHQwLCAzZgotI2lmZGVmIENPTkZJR19DT01QQVQKLQlSRUdfTCBz MCwgUFRfU1RBVFVTKHNwKQotCXNybGkgczAsIHMwLCBTUl9VWExfU0hJRlQKLQlhbmRpIHMwLCBz MCwgKFNSX1VYTCA+PiBTUl9VWExfU0hJRlQpCi0JbGkgdDAsIChTUl9VWExfMzIgPj4gU1JfVVhM X1NISUZUKQotCXN1YiB0MCwgczAsIHQwCi0JYm5leiB0MCwgMWYKLQotCS8qIENhbGwgY29tcGF0 X3N5c2NhbGwgKi8KLQlsYSBzMCwgY29tcGF0X3N5c19jYWxsX3RhYmxlCi0JaiAyZgotMToKLSNl bmRpZgotCS8qIENhbGwgc3lzY2FsbCAqLwotCWxhIHMwLCBzeXNfY2FsbF90YWJsZQotMjoKLQlz bGxpIHQwLCBhNywgUklTQ1ZfTEdQVFIKLQlhZGQgczAsIHMwLCB0MAotCVJFR19MIHMwLCAwKHMw KQotMzoKLQlqYWxyIHMwCi0KLXJldF9mcm9tX3N5c2NhbGw6Ci0JLyogU2V0IHVzZXIgYTAgdG8g a2VybmVsIGEwICovCi0JUkVHX1MgYTAsIFBUX0EwKHNwKQotCS8qCi0JICogV2UgZGlkbid0IGV4 ZWN1dGUgdGhlIGFjdHVhbCBzeXNjYWxsLgotCSAqIFNlY2NvbXAgYWxyZWFkeSBzZXQgcmV0dXJu IHZhbHVlIGZvciB0aGUgY3VycmVudCB0YXNrIHB0X3JlZ3MuCi0JICogKElmIGl0IHdhcyBjb25m aWd1cmVkIHdpdGggU0VDQ09NUF9SRVRfRVJSTk8vVFJBQ0UpCi0JICovCi1yZXRfZnJvbV9zeXNj YWxsX3JlamVjdGVkOgotI2lmZGVmIENPTkZJR19ERUJVR19SU0VRCi0JbW92ZSBhMCwgc3AKLQlj YWxsIHJzZXFfc3lzY2FsbAotI2VuZGlmCi0JLyogVHJhY2Ugc3lzY2FsbHMsIGJ1dCBvbmx5IGlm IHJlcXVlc3RlZCBieSB0aGUgdXNlci4gKi8KLQlSRUdfTCB0MCwgVEFTS19USV9GTEFHUyh0cCkK LQlhbmRpIHQwLCB0MCwgX1RJRl9TWVNDQUxMX1dPUksKLQlibmV6IHQwLCBoYW5kbGVfc3lzY2Fs bF90cmFjZV9leGl0Ci0KKy8qCisgKiBUaGUgcmV0X2Zyb21fZXhjZXB0aW9uIG11c3QgYmUgY2Fs bGVkIHdpdGggaW50ZXJydXB0IGRpc2FibGVkLiBIZXJlIGlzIHRoZQorICogY2FsbGVyIGxpc3Q6 CisgKiAgLSBoYW5kbGVfZXhjZXB0aW9uCisgKiAgLSByZXRfZnJvbV9mb3JrCisgKiAgLSByZXRf ZnJvbV9rZXJuZWxfdGhyZWFkCisgKi8KIFNZTV9DT0RFX1NUQVJUX05PQUxJR04ocmV0X2Zyb21f ZXhjZXB0aW9uKQogCVJFR19MIHMwLCBQVF9TVEFUVVMoc3ApCi0JY3NyYyBDU1JfU1RBVFVTLCBT Ul9JRQotI2lmZGVmIENPTkZJR19UUkFDRV9JUlFGTEFHUwotCWNhbGwgX190cmFjZV9oYXJkaXJx c19vZmYKLSNlbmRpZgogI2lmZGVmIENPTkZJR19SSVNDVl9NX01PREUKIAkvKiB0aGUgTVBQIHZh bHVlIGlzIHRvbyBsYXJnZSB0byBiZSB1c2VkIGFzIGFuIGltbWVkaWF0ZSBhcmcgZm9yIGFkZGkg Ki8KIAlsaSB0MCwgU1JfTVBQCkBAIC0yNjEsMTcgKzE0Myw3IEBAIFNZTV9DT0RFX1NUQVJUX05P QUxJR04ocmV0X2Zyb21fZXhjZXB0aW9uKQogI2Vsc2UKIAlhbmRpIHMwLCBzMCwgU1JfU1BQCiAj ZW5kaWYKLQlibmV6IHMwLCByZXN1bWVfa2VybmVsCi1TWU1fQ09ERV9FTkQocmV0X2Zyb21fZXhj ZXB0aW9uKQotCi0JLyogSW50ZXJydXB0cyBtdXN0IGJlIGRpc2FibGVkIGhlcmUgc28gZmxhZ3Mg YXJlIGNoZWNrZWQgYXRvbWljYWxseSAqLwotCVJFR19MIHMwLCBUQVNLX1RJX0ZMQUdTKHRwKSAv KiBjdXJyZW50X3RocmVhZF9pbmZvLT5mbGFncyAqLwotCWFuZGkgczEsIHMwLCBfVElGX1dPUktf TUFTSwotCWJuZXogczEsIHJlc3VtZV91c2Vyc3BhY2Vfc2xvdwotcmVzdW1lX3VzZXJzcGFjZToK LSNpZmRlZiBDT05GSUdfQ09OVEVYVF9UUkFDS0lOR19VU0VSCi0JY2FsbCB1c2VyX2VudGVyX2Nh bGxhYmxlCi0jZW5kaWYKKwlibmV6IHMwLCAxZgogCiAJLyogU2F2ZSB1bndvdW5kIGtlcm5lbCBz dGFjayBwb2ludGVyIGluIHRocmVhZF9pbmZvICovCiAJYWRkaSBzMCwgc3AsIFBUX1NJWkVfT05f U1RBQ0sKQEAgLTI4MiwxOCArMTU0LDcgQEAgcmVzdW1lX3VzZXJzcGFjZToKIAkgKiBzdHJ1Y3R1 cmVzIGFnYWluLgogCSAqLwogCWNzcncgQ1NSX1NDUkFUQ0gsIHRwCi0KLXJlc3RvcmVfYWxsOgot I2lmZGVmIENPTkZJR19UUkFDRV9JUlFGTEFHUwotCVJFR19MIHMxLCBQVF9TVEFUVVMoc3ApCi0J YW5kaSB0MCwgczEsIFNSX1BJRQotCWJlcXogdDAsIDFmCi0JY2FsbCBfX3RyYWNlX2hhcmRpcnFz X29uCi0JaiAyZgogMToKLQljYWxsIF9fdHJhY2VfaGFyZGlycXNfb2ZmCi0yOgotI2VuZGlmCiAJ UkVHX0wgYTAsIFBUX1NUQVRVUyhzcCkKIAkvKgogCSAqIFRoZSBjdXJyZW50IGxvYWQgcmVzZXJ2 YXRpb24gaXMgZWZmZWN0aXZlbHkgcGFydCBvZiB0aGUgcHJvY2Vzc29yJ3MKQEAgLTM1Niw0NyAr MjE3LDEwIEBAIHJlc3RvcmVfYWxsOgogI2Vsc2UKIAlzcmV0CiAjZW5kaWYKLQotI2lmIElTX0VO QUJMRUQoQ09ORklHX1BSRUVNUFRJT04pCi1yZXN1bWVfa2VybmVsOgotCVJFR19MIHMwLCBUQVNL X1RJX1BSRUVNUFRfQ09VTlQodHApCi0JYm5leiBzMCwgcmVzdG9yZV9hbGwKLQlSRUdfTCBzMCwg VEFTS19USV9GTEFHUyh0cCkKLQlhbmRpIHMwLCBzMCwgX1RJRl9ORUVEX1JFU0NIRUQKLQliZXF6 IHMwLCByZXN0b3JlX2FsbAotCWNhbGwgcHJlZW1wdF9zY2hlZHVsZV9pcnEKLQlqIHJlc3RvcmVf YWxsCi0jZW5kaWYKLQotcmVzdW1lX3VzZXJzcGFjZV9zbG93OgotCS8qIEVudGVyIHNsb3cgcGF0 aCBmb3Igc3VwcGxlbWVudGFyeSBwcm9jZXNzaW5nICovCi0JbW92ZSBhMCwgc3AgLyogcHRfcmVn cyAqLwotCW1vdmUgYTEsIHMwIC8qIGN1cnJlbnRfdGhyZWFkX2luZm8tPmZsYWdzICovCi0JY2Fs bCBkb193b3JrX3BlbmRpbmcKLQlqIHJlc3VtZV91c2Vyc3BhY2UKLQotLyogU2xvdyBwYXRocyBm b3IgcHRyYWNlLiAqLwotaGFuZGxlX3N5c2NhbGxfdHJhY2VfZW50ZXI6Ci0JbW92ZSBhMCwgc3AK LQljYWxsIGRvX3N5c2NhbGxfdHJhY2VfZW50ZXIKLQltb3ZlIHQwLCBhMAotCVJFR19MIGEwLCBQ VF9BMChzcCkKLQlSRUdfTCBhMSwgUFRfQTEoc3ApCi0JUkVHX0wgYTIsIFBUX0EyKHNwKQotCVJF R19MIGEzLCBQVF9BMyhzcCkKLQlSRUdfTCBhNCwgUFRfQTQoc3ApCi0JUkVHX0wgYTUsIFBUX0E1 KHNwKQotCVJFR19MIGE2LCBQVF9BNihzcCkKLQlSRUdfTCBhNywgUFRfQTcoc3ApCi0JYm5leiB0 MCwgcmV0X2Zyb21fc3lzY2FsbF9yZWplY3RlZAotCWogY2hlY2tfc3lzY2FsbF9ucgotaGFuZGxl X3N5c2NhbGxfdHJhY2VfZXhpdDoKLQltb3ZlIGEwLCBzcAotCWNhbGwgZG9fc3lzY2FsbF90cmFj ZV9leGl0Ci0JaiByZXRfZnJvbV9leGNlcHRpb24KK1NZTV9DT0RFX0VORChyZXRfZnJvbV9leGNl cHRpb24pCiAKICNpZmRlZiBDT05GSUdfVk1BUF9TVEFDSwotaGFuZGxlX2tlcm5lbF9zdGFja19v dmVyZmxvdzoKK1NZTV9DT0RFX1NUQVJUX0xPQ0FMKGhhbmRsZV9rZXJuZWxfc3RhY2tfb3ZlcmZs b3cpCiAJLyoKIAkgKiBUYWtlcyB0aGUgcHN1ZWRvLXNwaW5sb2NrIGZvciB0aGUgc2hhZG93IHN0 YWNrLCBpbiBjYXNlIG11bHRpcGxlCiAJICogaGFydHMgYXJlIGNvbmN1cnJlbnRseSBvdmVyZmxv d2luZyB0aGVpciBrZXJuZWwgc3RhY2tzLiAgV2UgY291bGQKQEAgLTUwNSwyMyArMzI5LDI1IEBA IHJlc3RvcmVfY2FsbGVyX3JlZzoKIAlSRUdfUyBzNSwgUFRfVFAoc3ApCiAJbW92ZSBhMCwgc3AK IAl0YWlsIGhhbmRsZV9iYWRfc3RhY2sKK1NZTV9DT0RFX0VORChoYW5kbGVfa2VybmVsX3N0YWNr X292ZXJmbG93KQogI2VuZGlmCiAKLUVORChoYW5kbGVfZXhjZXB0aW9uKQotCi1FTlRSWShyZXRf ZnJvbV9mb3JrKQorU1lNX0NPREVfU1RBUlQocmV0X2Zyb21fZm9yaykKKwljYWxsIHNjaGVkdWxl X3RhaWwKKwltb3ZlIGEwLCBzcCAvKiBwdF9yZWdzICovCiAJbGEgcmEsIHJldF9mcm9tX2V4Y2Vw dGlvbgotCXRhaWwgc2NoZWR1bGVfdGFpbAotRU5EUFJPQyhyZXRfZnJvbV9mb3JrKQorCXRhaWwg c3lzY2FsbF9leGl0X3RvX3VzZXJfbW9kZQorU1lNX0NPREVfRU5EKHJldF9mcm9tX2ZvcmspCiAK LUVOVFJZKHJldF9mcm9tX2tlcm5lbF90aHJlYWQpCitTWU1fQ09ERV9TVEFSVChyZXRfZnJvbV9r ZXJuZWxfdGhyZWFkKQogCWNhbGwgc2NoZWR1bGVfdGFpbAogCS8qIENhbGwgZm4oYXJnKSAqLwot CWxhIHJhLCByZXRfZnJvbV9leGNlcHRpb24KIAltb3ZlIGEwLCBzMQotCWpyIHMwCi1FTkRQUk9D KHJldF9mcm9tX2tlcm5lbF90aHJlYWQpCi0KKwlqYWxyIHMwCisJbW92ZSBhMCwgc3AgLyogcHRf cmVncyAqLworCWxhIHJhLCByZXRfZnJvbV9leGNlcHRpb24KKwl0YWlsIHN5c2NhbGxfZXhpdF90 b191c2VyX21vZGUKK1NZTV9DT0RFX0VORChyZXRfZnJvbV9rZXJuZWxfdGhyZWFkKQogCiAvKgog ICogSW50ZWdlciByZWdpc3RlciBjb250ZXh0IHN3aXRjaApAQCAtNTMzLDcgKzM1OSw3IEBAIEVO RFBST0MocmV0X2Zyb21fa2VybmVsX3RocmVhZCkKICAqIFRoZSB2YWx1ZSBvZiBhMCBhbmQgYTEg bXVzdCBiZSBwcmVzZXJ2ZWQgYnkgdGhpcyBmdW5jdGlvbiwgYXMgdGhhdCdzIGhvdwogICogYXJn dW1lbnRzIGFyZSBwYXNzZWQgdG8gc2NoZWR1bGVfdGFpbC4KICAqLwotRU5UUlkoX19zd2l0Y2hf dG8pCitTWU1fRlVOQ19TVEFSVChfX3N3aXRjaF90bykKIAkvKiBTYXZlIGNvbnRleHQgaW50byBw cmV2LT50aHJlYWQgKi8KIAlsaSAgICBhNCwgIFRBU0tfVEhSRUFEX1JBCiAJYWRkICAgYTMsIGEw LCBhNApAQCAtNTcwLDcgKzM5Niw3IEBAIEVOVFJZKF9fc3dpdGNoX3RvKQogCS8qIFRoZSBvZmZz ZXQgb2YgdGhyZWFkX2luZm8gaW4gdGFza19zdHJ1Y3QgaXMgemVyby4gKi8KIAltb3ZlIHRwLCBh MQogCXJldAotRU5EUFJPQyhfX3N3aXRjaF90bykKK1NZTV9GVU5DX0VORChfX3N3aXRjaF90bykK IAogI2lmbmRlZiBDT05GSUdfTU1VCiAjZGVmaW5lIGRvX3BhZ2VfZmF1bHQgZG9fdHJhcF91bmtu b3duCkBAIC01NzksNyArNDA1LDcgQEAgRU5EUFJPQyhfX3N3aXRjaF90bykKIAkuc2VjdGlvbiAi LnJvZGF0YSIKIAkuYWxpZ24gTEdSRUcKIAkvKiBFeGNlcHRpb24gdmVjdG9yIHRhYmxlICovCi1F TlRSWShleGNwX3ZlY3RfdGFibGUpCitTWU1fQ09ERV9TVEFSVChleGNwX3ZlY3RfdGFibGUpCiAJ UklTQ1ZfUFRSIGRvX3RyYXBfaW5zbl9taXNhbGlnbmVkCiAJQUxUX0lOU05fRkFVTFQoUklTQ1Zf UFRSIGRvX3RyYXBfaW5zbl9mYXVsdCkKIAlSSVNDVl9QVFIgZG9fdHJhcF9pbnNuX2lsbGVnYWwK QEAgLTU4OCw3ICs0MTQsNyBAQCBFTlRSWShleGNwX3ZlY3RfdGFibGUpCiAJUklTQ1ZfUFRSIGRv X3RyYXBfbG9hZF9mYXVsdAogCVJJU0NWX1BUUiBkb190cmFwX3N0b3JlX21pc2FsaWduZWQKIAlS SVNDVl9QVFIgZG9fdHJhcF9zdG9yZV9mYXVsdAotCVJJU0NWX1BUUiBkb190cmFwX2VjYWxsX3Ug Lyogc3lzdGVtIGNhbGwsIGdldHMgaW50ZXJjZXB0ZWQgKi8KKwlSSVNDVl9QVFIgZG9fdHJhcF9l Y2FsbF91IC8qIHN5c3RlbSBjYWxsICovCiAJUklTQ1ZfUFRSIGRvX3RyYXBfZWNhbGxfcwogCVJJ U0NWX1BUUiBkb190cmFwX3Vua25vd24KIAlSSVNDVl9QVFIgZG9fdHJhcF9lY2FsbF9tCkBAIC01 OTgsMTEgKzQyNCwxMSBAQCBFTlRSWShleGNwX3ZlY3RfdGFibGUpCiAJUklTQ1ZfUFRSIGRvX3Ry YXBfdW5rbm93bgogCVJJU0NWX1BUUiBkb19wYWdlX2ZhdWx0ICAgLyogc3RvcmUgcGFnZSBmYXVs dCAqLwogZXhjcF92ZWN0X3RhYmxlX2VuZDoKLUVORChleGNwX3ZlY3RfdGFibGUpCitTWU1fQ09E RV9FTkQoZXhjcF92ZWN0X3RhYmxlKQogCiAjaWZuZGVmIENPTkZJR19NTVUKLUVOVFJZKF9fdXNl cl9ydF9zaWdyZXR1cm4pCitTWU1fQ09ERV9TVEFSVChfX3VzZXJfcnRfc2lncmV0dXJuKQogCWxp IGE3LCBfX05SX3J0X3NpZ3JldHVybgogCXNjYWxsCi1FTkQoX191c2VyX3J0X3NpZ3JldHVybikK K1NZTV9DT0RFX0VORChfX3VzZXJfcnRfc2lncmV0dXJuKQogI2VuZGlmCmRpZmYgLS1naXQgYS9h cmNoL3Jpc2N2L2tlcm5lbC9wdHJhY2UuYyBiL2FyY2gvcmlzY3Yva2VybmVsL3B0cmFjZS5jCmlu ZGV4IDQ0ZjRiMWNhMzE1ZC4uMjNjNDhiMTRhMGU3IDEwMDY0NAotLS0gYS9hcmNoL3Jpc2N2L2tl cm5lbC9wdHJhY2UuYworKysgYi9hcmNoL3Jpc2N2L2tlcm5lbC9wdHJhY2UuYwpAQCAtMTksOSAr MTksNiBAQAogI2luY2x1ZGUgPGxpbnV4L3NjaGVkLmg+CiAjaW5jbHVkZSA8bGludXgvc2NoZWQv dGFza19zdGFjay5oPgogCi0jZGVmaW5lIENSRUFURV9UUkFDRV9QT0lOVFMKLSNpbmNsdWRlIDx0 cmFjZS9ldmVudHMvc3lzY2FsbHMuaD4KLQogZW51bSByaXNjdl9yZWdzZXQgewogCVJFR1NFVF9Y LAogI2lmZGVmIENPTkZJR19GUFUKQEAgLTIyOCw0NiArMjI1LDYgQEAgbG9uZyBhcmNoX3B0cmFj ZShzdHJ1Y3QgdGFza19zdHJ1Y3QgKmNoaWxkLCBsb25nIHJlcXVlc3QsCiAJcmV0dXJuIHJldDsK IH0KIAotLyoKLSAqIEFsbG93cyBQVFJBQ0VfU1lTQ0FMTCB0byB3b3JrLiAgVGhlc2UgYXJlIGNh bGxlZCBmcm9tIGVudHJ5LlMgaW4KLSAqIHtoYW5kbGUscmV0X2Zyb219X3N5c2NhbGwuCi0gKi8K LV9fdmlzaWJsZSBpbnQgZG9fc3lzY2FsbF90cmFjZV9lbnRlcihzdHJ1Y3QgcHRfcmVncyAqcmVn cykKLXsKLQlpZiAodGVzdF90aHJlYWRfZmxhZyhUSUZfU1lTQ0FMTF9UUkFDRSkpCi0JCWlmIChw dHJhY2VfcmVwb3J0X3N5c2NhbGxfZW50cnkocmVncykpCi0JCQlyZXR1cm4gLTE7Ci0KLQkvKgot CSAqIERvIHRoZSBzZWN1cmUgY29tcHV0aW5nIGFmdGVyIHB0cmFjZTsgZmFpbHVyZXMgc2hvdWxk IGJlIGZhc3QuCi0JICogSWYgdGhpcyBmYWlscyB3ZSBtaWdodCBoYXZlIHJldHVybiB2YWx1ZSBp biBhMCBmcm9tIHNlY2NvbXAKLQkgKiAodmlhIFNFQ0NPTVBfUkVUX0VSUk5PL1RSQUNFKS4KLQkg Ki8KLQlpZiAoc2VjdXJlX2NvbXB1dGluZygpID09IC0xKQotCQlyZXR1cm4gLTE7Ci0KLSNpZmRl ZiBDT05GSUdfSEFWRV9TWVNDQUxMX1RSQUNFUE9JTlRTCi0JaWYgKHRlc3RfdGhyZWFkX2ZsYWco VElGX1NZU0NBTExfVFJBQ0VQT0lOVCkpCi0JCXRyYWNlX3N5c19lbnRlcihyZWdzLCBzeXNjYWxs X2dldF9ucihjdXJyZW50LCByZWdzKSk7Ci0jZW5kaWYKLQotCWF1ZGl0X3N5c2NhbGxfZW50cnko cmVncy0+YTcsIHJlZ3MtPmEwLCByZWdzLT5hMSwgcmVncy0+YTIsIHJlZ3MtPmEzKTsKLQlyZXR1 cm4gMDsKLX0KLQotX192aXNpYmxlIHZvaWQgZG9fc3lzY2FsbF90cmFjZV9leGl0KHN0cnVjdCBw dF9yZWdzICpyZWdzKQotewotCWF1ZGl0X3N5c2NhbGxfZXhpdChyZWdzKTsKLQotCWlmICh0ZXN0 X3RocmVhZF9mbGFnKFRJRl9TWVNDQUxMX1RSQUNFKSkKLQkJcHRyYWNlX3JlcG9ydF9zeXNjYWxs X2V4aXQocmVncywgMCk7Ci0KLSNpZmRlZiBDT05GSUdfSEFWRV9TWVNDQUxMX1RSQUNFUE9JTlRT Ci0JaWYgKHRlc3RfdGhyZWFkX2ZsYWcoVElGX1NZU0NBTExfVFJBQ0VQT0lOVCkpCi0JCXRyYWNl X3N5c19leGl0KHJlZ3MsIHJlZ3NfcmV0dXJuX3ZhbHVlKHJlZ3MpKTsKLSNlbmRpZgotfQotCiAj aWZkZWYgQ09ORklHX0NPTVBBVAogc3RhdGljIGludCBjb21wYXRfcmlzY3ZfZ3ByX2dldChzdHJ1 Y3QgdGFza19zdHJ1Y3QgKnRhcmdldCwKIAkJCQljb25zdCBzdHJ1Y3QgdXNlcl9yZWdzZXQgKnJl Z3NldCwKZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL3NpZ25hbC5jIGIvYXJjaC9yaXNj di9rZXJuZWwvc2lnbmFsLmMKaW5kZXggYmZiMmFmYTQxMzVmLi5hN2I2YmQwZGY0OTcgMTAwNjQ0 Ci0tLSBhL2FyY2gvcmlzY3Yva2VybmVsL3NpZ25hbC5jCisrKyBiL2FyY2gvcmlzY3Yva2VybmVs L3NpZ25hbC5jCkBAIC0yNzQsNyArMjc0LDcgQEAgc3RhdGljIHZvaWQgaGFuZGxlX3NpZ25hbChz dHJ1Y3Qga3NpZ25hbCAqa3NpZywgc3RydWN0IHB0X3JlZ3MgKnJlZ3MpCiAJc2lnbmFsX3NldHVw X2RvbmUocmV0LCBrc2lnLCAwKTsKIH0KIAotc3RhdGljIHZvaWQgZG9fc2lnbmFsKHN0cnVjdCBw dF9yZWdzICpyZWdzKQordm9pZCBhcmNoX2RvX3NpZ25hbF9vcl9yZXN0YXJ0KHN0cnVjdCBwdF9y ZWdzICpyZWdzKQogewogCXN0cnVjdCBrc2lnbmFsIGtzaWc7CiAKQEAgLTMxMSwyOSArMzExLDMg QEAgc3RhdGljIHZvaWQgZG9fc2lnbmFsKHN0cnVjdCBwdF9yZWdzICpyZWdzKQogCSAqLwogCXJl c3RvcmVfc2F2ZWRfc2lnbWFzaygpOwogfQotCi0vKgotICogSGFuZGxlIGFueSBwZW5kaW5nIHdv cmsgb24gdGhlIHJlc3VtZS10by11c2Vyc3BhY2UgcGF0aCwgYXMgaW5kaWNhdGVkIGJ5Ci0gKiBf VElGX1dPUktfTUFTSy4gRW50ZXJlZCBmcm9tIGFzc2VtYmx5IHdpdGggSVJRcyBvZmYuCi0gKi8K LWFzbWxpbmthZ2UgX192aXNpYmxlIHZvaWQgZG9fd29ya19wZW5kaW5nKHN0cnVjdCBwdF9yZWdz ICpyZWdzLAotCQkJCQkgIHVuc2lnbmVkIGxvbmcgdGhyZWFkX2luZm9fZmxhZ3MpCi17Ci0JZG8g ewotCQlpZiAodGhyZWFkX2luZm9fZmxhZ3MgJiBfVElGX05FRURfUkVTQ0hFRCkgewotCQkJc2No ZWR1bGUoKTsKLQkJfSBlbHNlIHsKLQkJCWxvY2FsX2lycV9lbmFibGUoKTsKLQkJCWlmICh0aHJl YWRfaW5mb19mbGFncyAmIF9USUZfVVBST0JFKQotCQkJCXVwcm9iZV9ub3RpZnlfcmVzdW1lKHJl Z3MpOwotCQkJLyogSGFuZGxlIHBlbmRpbmcgc2lnbmFsIGRlbGl2ZXJ5ICovCi0JCQlpZiAodGhy ZWFkX2luZm9fZmxhZ3MgJiAoX1RJRl9TSUdQRU5ESU5HIHwKLQkJCQkJCSBfVElGX05PVElGWV9T SUdOQUwpKQotCQkJCWRvX3NpZ25hbChyZWdzKTsKLQkJCWlmICh0aHJlYWRfaW5mb19mbGFncyAm IF9USUZfTk9USUZZX1JFU1VNRSkKLQkJCQlyZXN1bWVfdXNlcl9tb2RlX3dvcmsocmVncyk7Ci0J CX0KLQkJbG9jYWxfaXJxX2Rpc2FibGUoKTsKLQkJdGhyZWFkX2luZm9fZmxhZ3MgPSByZWFkX3Ro cmVhZF9mbGFncygpOwotCX0gd2hpbGUgKHRocmVhZF9pbmZvX2ZsYWdzICYgX1RJRl9XT1JLX01B U0spOwotfQpkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9rZXJuZWwvdHJhcHMuYyBiL2FyY2gvcmlz Y3Yva2VybmVsL3RyYXBzLmMKaW5kZXggOTZlYzc2YzU0ZmYyLi4zMDg1NWFjYWM4NTAgMTAwNjQ0 Ci0tLSBhL2FyY2gvcmlzY3Yva2VybmVsL3RyYXBzLmMKKysrIGIvYXJjaC9yaXNjdi9rZXJuZWwv dHJhcHMuYwpAQCAtMTcsMTIgKzE3LDE0IEBACiAjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+CiAj aW5jbHVkZSA8bGludXgvaXJxLmg+CiAjaW5jbHVkZSA8bGludXgva2V4ZWMuaD4KKyNpbmNsdWRl IDxsaW51eC9lbnRyeS1jb21tb24uaD4KIAogI2luY2x1ZGUgPGFzbS9hc20tcHJvdG90eXBlcy5o PgogI2luY2x1ZGUgPGFzbS9idWcuaD4KICNpbmNsdWRlIDxhc20vY3NyLmg+CiAjaW5jbHVkZSA8 YXNtL3Byb2Nlc3Nvci5oPgogI2luY2x1ZGUgPGFzbS9wdHJhY2UuaD4KKyNpbmNsdWRlIDxhc20v c3lzY2FsbC5oPgogI2luY2x1ZGUgPGFzbS90aHJlYWRfaW5mby5oPgogCiBpbnQgc2hvd191bmhh bmRsZWRfc2lnbmFscyA9IDE7CkBAIC05OSwxMCArMTAxLDE4IEBAIHN0YXRpYyB2b2lkIGRvX3Ry YXBfZXJyb3Ioc3RydWN0IHB0X3JlZ3MgKnJlZ3MsIGludCBzaWdubywgaW50IGNvZGUsCiAjZWxz ZQogI2RlZmluZSBfX3RyYXBfc2VjdGlvbiBub2luc3RyCiAjZW5kaWYKLSNkZWZpbmUgRE9fRVJS T1JfSU5GTyhuYW1lLCBzaWdubywgY29kZSwgc3RyKQkJCQlcCi1hc21saW5rYWdlIF9fdmlzaWJs ZSBfX3RyYXBfc2VjdGlvbiB2b2lkIG5hbWUoc3RydWN0IHB0X3JlZ3MgKnJlZ3MpCVwKLXsJCQkJ CQkJCQlcCi0JZG9fdHJhcF9lcnJvcihyZWdzLCBzaWdubywgY29kZSwgcmVncy0+ZXBjLCAiT29w cyAtICIgc3RyKTsJXAorI2RlZmluZSBET19FUlJPUl9JTkZPKG5hbWUsIHNpZ25vLCBjb2RlLCBz dHIpCQkJCQlcCithc21saW5rYWdlIF9fdmlzaWJsZSBfX3RyYXBfc2VjdGlvbiB2b2lkIG5hbWUo c3RydWN0IHB0X3JlZ3MgKnJlZ3MpCQlcCit7CQkJCQkJCQkJCVwKKwlpZiAodXNlcl9tb2RlKHJl Z3MpKSB7CQkJCQkJCVwKKwkJaXJxZW50cnlfZW50ZXJfZnJvbV91c2VyX21vZGUocmVncyk7CQkJ CVwKKwkJZG9fdHJhcF9lcnJvcihyZWdzLCBzaWdubywgY29kZSwgcmVncy0+ZXBjLCAiT29wcyAt ICIgc3RyKTsJXAorCQlpcnFlbnRyeV9leGl0X3RvX3VzZXJfbW9kZShyZWdzKTsJCQkJXAorCX0g ZWxzZSB7CQkJCQkJCQlcCisJCWlycWVudHJ5X3N0YXRlX3Qgc3RhdGUgPSBpcnFlbnRyeV9ubWlf ZW50ZXIocmVncyk7CQlcCisJCWRvX3RyYXBfZXJyb3IocmVncywgc2lnbm8sIGNvZGUsIHJlZ3Mt PmVwYywgIk9vcHMgLSAiIHN0cik7CVwKKwkJaXJxZW50cnlfbm1pX2V4aXQocmVncywgc3RhdGUp OwkJCQkJXAorCX0JCQkJCQkJCQlcCiB9CiAKIERPX0VSUk9SX0lORk8oZG9fdHJhcF91bmtub3du LApAQCAtMTI0LDI2ICsxMzQsNTAgQEAgRE9fRVJST1JfSU5GTyhkb190cmFwX3N0b3JlX21pc2Fs aWduZWQsCiBpbnQgaGFuZGxlX21pc2FsaWduZWRfbG9hZChzdHJ1Y3QgcHRfcmVncyAqcmVncyk7 CiBpbnQgaGFuZGxlX21pc2FsaWduZWRfc3RvcmUoc3RydWN0IHB0X3JlZ3MgKnJlZ3MpOwogCi1h c21saW5rYWdlIHZvaWQgX190cmFwX3NlY3Rpb24gZG9fdHJhcF9sb2FkX21pc2FsaWduZWQoc3Ry dWN0IHB0X3JlZ3MgKnJlZ3MpCithc21saW5rYWdlIF9fdmlzaWJsZSBfX3RyYXBfc2VjdGlvbiB2 b2lkIGRvX3RyYXBfbG9hZF9taXNhbGlnbmVkKHN0cnVjdCBwdF9yZWdzICpyZWdzKQogewotCWlm ICghaGFuZGxlX21pc2FsaWduZWRfbG9hZChyZWdzKSkKLQkJcmV0dXJuOwotCWRvX3RyYXBfZXJy b3IocmVncywgU0lHQlVTLCBCVVNfQURSQUxOLCByZWdzLT5lcGMsCi0JCSAgICAgICJPb3BzIC0g bG9hZCBhZGRyZXNzIG1pc2FsaWduZWQiKTsKKwlpZiAodXNlcl9tb2RlKHJlZ3MpKSB7CisJCWly cWVudHJ5X2VudGVyX2Zyb21fdXNlcl9tb2RlKHJlZ3MpOworCisJCWlmIChoYW5kbGVfbWlzYWxp Z25lZF9sb2FkKHJlZ3MpKQorCQkJZG9fdHJhcF9lcnJvcihyZWdzLCBTSUdCVVMsIEJVU19BRFJB TE4sIHJlZ3MtPmVwYywKKwkJCSAgICAgICJPb3BzIC0gbG9hZCBhZGRyZXNzIG1pc2FsaWduZWQi KTsKKworCQlpcnFlbnRyeV9leGl0X3RvX3VzZXJfbW9kZShyZWdzKTsKKwl9IGVsc2UgeworCQlp cnFlbnRyeV9zdGF0ZV90IHN0YXRlID0gaXJxZW50cnlfbm1pX2VudGVyKHJlZ3MpOworCisJCWlm IChoYW5kbGVfbWlzYWxpZ25lZF9sb2FkKHJlZ3MpKQorCQkJZG9fdHJhcF9lcnJvcihyZWdzLCBT SUdCVVMsIEJVU19BRFJBTE4sIHJlZ3MtPmVwYywKKwkJCSAgICAgICJPb3BzIC0gbG9hZCBhZGRy ZXNzIG1pc2FsaWduZWQiKTsKKworCQlpcnFlbnRyeV9ubWlfZXhpdChyZWdzLCBzdGF0ZSk7CisJ fQogfQogCi1hc21saW5rYWdlIHZvaWQgX190cmFwX3NlY3Rpb24gZG9fdHJhcF9zdG9yZV9taXNh bGlnbmVkKHN0cnVjdCBwdF9yZWdzICpyZWdzKQorYXNtbGlua2FnZSBfX3Zpc2libGUgX190cmFw X3NlY3Rpb24gdm9pZCBkb190cmFwX3N0b3JlX21pc2FsaWduZWQoc3RydWN0IHB0X3JlZ3MgKnJl Z3MpCiB7Ci0JaWYgKCFoYW5kbGVfbWlzYWxpZ25lZF9zdG9yZShyZWdzKSkKLQkJcmV0dXJuOwot CWRvX3RyYXBfZXJyb3IocmVncywgU0lHQlVTLCBCVVNfQURSQUxOLCByZWdzLT5lcGMsCi0JCSAg ICAgICJPb3BzIC0gc3RvcmUgKG9yIEFNTykgYWRkcmVzcyBtaXNhbGlnbmVkIik7CisJaWYgKHVz ZXJfbW9kZShyZWdzKSkgeworCQlpcnFlbnRyeV9lbnRlcl9mcm9tX3VzZXJfbW9kZShyZWdzKTsK KworCQlpZiAoaGFuZGxlX21pc2FsaWduZWRfc3RvcmUocmVncykpCisJCQlkb190cmFwX2Vycm9y KHJlZ3MsIFNJR0JVUywgQlVTX0FEUkFMTiwgcmVncy0+ZXBjLAorCQkJCSJPb3BzIC0gc3RvcmUg KG9yIEFNTykgYWRkcmVzcyBtaXNhbGlnbmVkIik7CisKKwkJaXJxZW50cnlfZXhpdF90b191c2Vy X21vZGUocmVncyk7CisJfSBlbHNlIHsKKwkJaXJxZW50cnlfc3RhdGVfdCBzdGF0ZSA9IGlycWVu dHJ5X25taV9lbnRlcihyZWdzKTsKKworCQlpZiAoaGFuZGxlX21pc2FsaWduZWRfc3RvcmUocmVn cykpCisJCQlkb190cmFwX2Vycm9yKHJlZ3MsIFNJR0JVUywgQlVTX0FEUkFMTiwgcmVncy0+ZXBj LAorCQkJCSJPb3BzIC0gc3RvcmUgKG9yIEFNTykgYWRkcmVzcyBtaXNhbGlnbmVkIik7CisKKwkJ aXJxZW50cnlfbm1pX2V4aXQocmVncywgc3RhdGUpOworCX0KIH0KICNlbmRpZgogRE9fRVJST1Jf SU5GTyhkb190cmFwX3N0b3JlX2ZhdWx0LAogCVNJR1NFR1YsIFNFR1ZfQUNDRVJSLCAic3RvcmUg KG9yIEFNTykgYWNjZXNzIGZhdWx0Iik7Ci1ET19FUlJPUl9JTkZPKGRvX3RyYXBfZWNhbGxfdSwK LQlTSUdJTEwsIElMTF9JTExUUlAsICJlbnZpcm9ubWVudCBjYWxsIGZyb20gVS1tb2RlIik7CiBE T19FUlJPUl9JTkZPKGRvX3RyYXBfZWNhbGxfcywKIAlTSUdJTEwsIElMTF9JTExUUlAsICJlbnZp cm9ubWVudCBjYWxsIGZyb20gUy1tb2RlIik7CiBET19FUlJPUl9JTkZPKGRvX3RyYXBfZWNhbGxf bSwKQEAgLTE1OSw3ICsxOTMsNyBAQCBzdGF0aWMgaW5saW5lIHVuc2lnbmVkIGxvbmcgZ2V0X2Jy ZWFrX2luc25fbGVuZ3RoKHVuc2lnbmVkIGxvbmcgcGMpCiAJcmV0dXJuIEdFVF9JTlNOX0xFTkdU SChpbnNuKTsKIH0KIAotYXNtbGlua2FnZSBfX3Zpc2libGUgX190cmFwX3NlY3Rpb24gdm9pZCBk b190cmFwX2JyZWFrKHN0cnVjdCBwdF9yZWdzICpyZWdzKQordm9pZCBoYW5kbGVfYnJlYWsoc3Ry dWN0IHB0X3JlZ3MgKnJlZ3MpCiB7CiAjaWZkZWYgQ09ORklHX0tQUk9CRVMKIAlpZiAoa3Byb2Jl X3NpbmdsZV9zdGVwX2hhbmRsZXIocmVncykpCkBAIC0xODksNyArMjIzLDY4IEBAIGFzbWxpbmth Z2UgX192aXNpYmxlIF9fdHJhcF9zZWN0aW9uIHZvaWQgZG9fdHJhcF9icmVhayhzdHJ1Y3QgcHRf cmVncyAqcmVncykKIAllbHNlCiAJCWRpZShyZWdzLCAiS2VybmVsIEJVRyIpOwogfQotTk9LUFJP QkVfU1lNQk9MKGRvX3RyYXBfYnJlYWspOworCithc21saW5rYWdlIF9fdmlzaWJsZSBfX3RyYXBf c2VjdGlvbiB2b2lkIGRvX3RyYXBfYnJlYWsoc3RydWN0IHB0X3JlZ3MgKnJlZ3MpCit7CisJaWYg KHVzZXJfbW9kZShyZWdzKSkgeworCQlpcnFlbnRyeV9lbnRlcl9mcm9tX3VzZXJfbW9kZShyZWdz KTsKKworCQloYW5kbGVfYnJlYWsocmVncyk7CisKKwkJaXJxZW50cnlfZXhpdF90b191c2VyX21v ZGUocmVncyk7CisJfSBlbHNlIHsKKwkJaXJxZW50cnlfc3RhdGVfdCBzdGF0ZSA9IGlycWVudHJ5 X25taV9lbnRlcihyZWdzKTsKKworCQloYW5kbGVfYnJlYWsocmVncyk7CisKKwkJaXJxZW50cnlf bm1pX2V4aXQocmVncywgc3RhdGUpOworCX0KK30KKworYXNtbGlua2FnZSBfX3Zpc2libGUgX190 cmFwX3NlY3Rpb24gdm9pZCBkb190cmFwX2VjYWxsX3Uoc3RydWN0IHB0X3JlZ3MgKnJlZ3MpCit7 CisJaWYgKHVzZXJfbW9kZShyZWdzKSkgeworCQlsb25nIHN5c2NhbGwgPSByZWdzLT5hNzsKKwkJ c3lzY2FsbCA9IHN5c2NhbGxfZW50ZXJfZnJvbV91c2VyX21vZGUocmVncywgc3lzY2FsbCk7CisK KwkJc3lzY2FsbF9oYW5kbGVyKHJlZ3MsICh1bG9uZylzeXNjYWxsKTsKKworCQlzeXNjYWxsX2V4 aXRfdG9fdXNlcl9tb2RlKHJlZ3MpOworCX0gZWxzZSB7CisJCWlycWVudHJ5X3N0YXRlX3Qgc3Rh dGUgPSBpcnFlbnRyeV9ubWlfZW50ZXIocmVncyk7CisKKwkJZG9fdHJhcF9lcnJvcihyZWdzLCBT SUdJTEwsIElMTF9JTExUUlAsIHJlZ3MtPmVwYywKKwkJCSJPb3BzIC0gZW52aXJvbm1lbnQgY2Fs bCBmcm9tIFUtbW9kZSIpOworCisJCWlycWVudHJ5X25taV9leGl0KHJlZ3MsIHN0YXRlKTsKKwl9 CisKK30KKworYXNtbGlua2FnZSBfX3Zpc2libGUgbm9pbnN0ciB2b2lkIGRvX3BhZ2VfZmF1bHQo c3RydWN0IHB0X3JlZ3MgKnJlZ3MpCit7CisJaXJxZW50cnlfc3RhdGVfdCBzdGF0ZSA9IGlycWVu dHJ5X2VudGVyKHJlZ3MpOworCisJaGFuZGxlX3BhZ2VfZmF1bHQocmVncyk7CisKKwlsb2NhbF9p cnFfZGlzYWJsZSgpOworCisJaXJxZW50cnlfZXhpdChyZWdzLCBzdGF0ZSk7Cit9CisKK2FzbWxp bmthZ2UgX192aXNpYmxlIG5vaW5zdHIgdm9pZCBkb19pcnEoc3RydWN0IHB0X3JlZ3MgKnJlZ3Mp Cit7CisJc3RydWN0IHB0X3JlZ3MgKm9sZF9yZWdzOworCWlycWVudHJ5X3N0YXRlX3Qgc3RhdGUg PSBpcnFlbnRyeV9lbnRlcihyZWdzKTsKKworCWlycV9lbnRlcl9yY3UoKTsKKwlvbGRfcmVncyA9 IHNldF9pcnFfcmVncyhyZWdzKTsKKwloYW5kbGVfYXJjaF9pcnEocmVncyk7CisJc2V0X2lycV9y ZWdzKG9sZF9yZWdzKTsKKwlpcnFfZXhpdF9yY3UoKTsKKworCWlycWVudHJ5X2V4aXQocmVncywg c3RhdGUpOworfQogCiAjaWZkZWYgQ09ORklHX0dFTkVSSUNfQlVHCiBpbnQgaXNfdmFsaWRfYnVn YWRkcih1bnNpZ25lZCBsb25nIHBjKQpkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9tbS9mYXVsdC5j IGIvYXJjaC9yaXNjdi9tbS9mYXVsdC5jCmluZGV4IGQ4NmY3Y2ViZDRhNy4uZTA0NTkzYzZjZmUz IDEwMDY0NAotLS0gYS9hcmNoL3Jpc2N2L21tL2ZhdWx0LmMKKysrIGIvYXJjaC9yaXNjdi9tbS9m YXVsdC5jCkBAIC0yMDQsNyArMjA0LDcgQEAgc3RhdGljIGlubGluZSBib29sIGFjY2Vzc19lcnJv cih1bnNpZ25lZCBsb25nIGNhdXNlLCBzdHJ1Y3Qgdm1fYXJlYV9zdHJ1Y3QgKnZtYSkKICAqIFRo aXMgcm91dGluZSBoYW5kbGVzIHBhZ2UgZmF1bHRzLiAgSXQgZGV0ZXJtaW5lcyB0aGUgYWRkcmVz cyBhbmQgdGhlCiAgKiBwcm9ibGVtLCBhbmQgdGhlbiBwYXNzZXMgaXQgb2ZmIHRvIG9uZSBvZiB0 aGUgYXBwcm9wcmlhdGUgcm91dGluZXMuCiAgKi8KLWFzbWxpbmthZ2Ugdm9pZCBkb19wYWdlX2Zh dWx0KHN0cnVjdCBwdF9yZWdzICpyZWdzKQordm9pZCBoYW5kbGVfcGFnZV9mYXVsdChzdHJ1Y3Qg cHRfcmVncyAqcmVncykKIHsKIAlzdHJ1Y3QgdGFza19zdHJ1Y3QgKnRzazsKIAlzdHJ1Y3Qgdm1f YXJlYV9zdHJ1Y3QgKnZtYTsKQEAgLTI1MSw3ICsyNTEsNyBAQCBhc21saW5rYWdlIHZvaWQgZG9f cGFnZV9mYXVsdChzdHJ1Y3QgcHRfcmVncyAqcmVncykKIAl9CiAjZW5kaWYKIAkvKiBFbmFibGUg aW50ZXJydXB0cyBpZiB0aGV5IHdlcmUgZW5hYmxlZCBpbiB0aGUgcGFyZW50IGNvbnRleHQuICov Ci0JaWYgKGxpa2VseShyZWdzLT5zdGF0dXMgJiBTUl9QSUUpKQorCWlmICghcmVnc19pcnFzX2Rp c2FibGVkKHJlZ3MpKQogCQlsb2NhbF9pcnFfZW5hYmxlKCk7CiAKIAkvKgpAQCAtMzUxLDQgKzM1 MSwzIEBAIGFzbWxpbmthZ2Ugdm9pZCBkb19wYWdlX2ZhdWx0KHN0cnVjdCBwdF9yZWdzICpyZWdz KQogCX0KIAlyZXR1cm47CiB9Ci1OT0tQUk9CRV9TWU1CT0woZG9fcGFnZV9mYXVsdCk7Ci0tIAoy LjM2LjEKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwps aW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpo dHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg==