Re: [PATCH] cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Fri, 06 Jan 2023 09:39:49 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> 'addr' that contains RAS UE register address is re-assigned to
> RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr
> variable to avoid the reassignment mistake.
> 
> Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support")
> Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Exactly what I expected. Thanks for the quick turn around.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

I'm working on adding multiple header log handling on top of your
code.  Will hopefully have something to share on that later in the week.

> ---
>  drivers/cxl/pci.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 33083a522fd1..258004f34281 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -554,8 +554,11 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>  
>  	/* If multiple errors, log header points to first error from ctrl reg */
>  	if (hweight32(status) > 1) {
> -		addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> -		fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(addr)));
> +		void __iomem *rcc_addr =
> +			cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
> +
> +		fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
> +				   readl(rcc_addr)));
>  	} else {
>  		fe = status;
>  	}
> 
>