From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F06BC3DA78 for ; Tue, 17 Jan 2023 14:56:29 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 183966942; Tue, 17 Jan 2023 15:55:37 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 183966942 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1673967387; bh=6lBt1qq7/VrsXRUsfkzS13rWWax7gI7bBxyiffF1l3c=; h=Date:From:To:Subject:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: Cc:From; b=uRJkUDRtpZ7BS05H2LIinJ1ieAO663C2fn8+4oyPc3LIqWiLVSrF1TWn77UZQeFiQ PYjxjWt3nvAsGNbMVznvEyIJslkwaHZGAGoelRYhQi7fOwV4y/qkthxRERlv3LsN+g 479KDOI2E9pJDb0NLjCLFwnyFuS/vRbK5Nc8b69U= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id BEC5EF8026D; Tue, 17 Jan 2023 15:55:36 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id F2917F8047B; Tue, 17 Jan 2023 15:55:34 +0100 (CET) Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 12E74F8022D for ; Tue, 17 Jan 2023 15:55:32 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 12E74F8022D Received: by mail-oa1-f51.google.com with SMTP id 586e51a60fabf-15027746720so32166738fac.13 for ; Tue, 17 Jan 2023 06:55:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=r0xOPUwMGbHKwlz1eX+ZfzIFwn/1MAHYgP6guftK2G0=; b=WpyeBmw6U4v3y1wXDtC/ikqGBTdIj8RaVoAebDY7RBSPbfnvTcJF6afwwDt5P9FRbq 3WNo9ILJb1Q7RViFB2llGyqKNWPUqh6qBYzcaby7w7p2g8kmW5soH+VuFdx9Xy2EGwA0 lpsC/a/EB+rdY2q7kMZYI4vaisp3CVrwSkOve8UCp78OzNIFIkBY7IIfZuJ7yPNghVst fp8wilhRkaapQl3ljz97Ei0JsjTLfb5PU23aCarVNSOZFr7TmAcNvYZUV+RiD9v6aIMk RnIFELujNG6okRCd6bCN1BpcyZ68f/QNoPh3W0NFeAnpmLlEndCkz7PEXEG0TuYQANGT As/w== X-Gm-Message-State: AFqh2kqpWzmssmRsBOZVayGj/xEY9uzAPRbMcH2SKCYwfKvOeYOlTCjD 39+vyr/A9j9pkEPrc+k6eQ== X-Google-Smtp-Source: AMrXdXsNUJ00dTOKvt2jfPMH4Ze0uTp6cmxdG4fza3JfdEkyhCZe9BD6Z//VMQY6JmDD12zrOOWqFg== X-Received: by 2002:a05:6870:2f02:b0:15f:3213:dfc6 with SMTP id qj2-20020a0568702f0200b0015f3213dfc6mr1901825oab.35.1673967331153; Tue, 17 Jan 2023 06:55:31 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0013ae5246449sm16348572oac.22.2023.01.17.06.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 06:55:30 -0800 (PST) Received: (nullmailer pid 3058299 invoked by uid 1000); Tue, 17 Jan 2023 14:55:29 -0000 Date: Tue, 17 Jan 2023 08:55:29 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v3 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230117145529.GA3044055-robh@kernel.org> References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230113103759.327698-2-herve.codina@bootlin.com> X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Michael Ellerman , Takashi Iwai , Liam Girdwood , Christophe Leroy , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Nicholas Piggin , Krzysztof Kozlowski , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. An odd line wrap length... > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++ > include/dt-bindings/soc/fsl,tsa.h | 13 + > 2 files changed, 273 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > new file mode 100644 > index 000000000000..eb17b6119abd > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > @@ -0,0 +1,260 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: | Don't need '|' if no formatting. > + The TSA is the time-slot assigner that can be found on some > + PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal > + serial controllers. Wrap at 80. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^tdm@[0-1]$': > + description: > + The TDM managed by this controller > + type: object additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 1 > + description: > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, > + Tx sync, Rx clock and Rx sync or use only two pins, > + Tx/Rx clock and Rx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four > + pins are used. With the 'fsl,common-rxtx-pins' property, > + two pins are used. > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + minItems: 2 > + maxItems: 4 > + > + fsl,mode: 'mode' is a bit vague. It's already used as well which can be a problem if there are differing types. (There's not in this case) > + $ref: /schemas/types.yaml#/definitions/string > + enum: [normal, echo, internal-loopback, control-loopback] > + default: normal > + description: | > + Operational mode: > + - normal: > + Normal operation > + - echo: > + Automatic echo. Rx data is resent on Tx > + - internal-loopback: > + The TDM transmitter is connected to the receiver. > + Data appears on Tx pin. > + - control-loopback: > + The TDM transmitter is connected to the receiver. > + The Tx pin is disconnected. > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the > + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the > + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + Data is sent on falling edge of the clock (and received on the > + rising edge). > + If 'clock-falling-edge' is not present, data is sent on the > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sample > + with e falling edge. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + fsl,tx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Tx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route to SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route to SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + fsl,rx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Rx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route from SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route from SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The destination serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + else: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + - description: External clock connected to L1TSYNC pin > + - description: External clock connected to L1TCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + - const: l1tsync > + - const: l1tclk As the names are the same, just the length varies between 2 or 4, move all this to the main definition and here just put constraints on the length. > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tsa@ae0 { > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "l1rsync", "l1rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h > new file mode 100644 > index 000000000000..2cc44e867dbe > --- /dev/null > +++ b/include/dt-bindings/soc/fsl,tsa.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H > +#define __DT_BINDINGS_SOC_FSL_TSA_H > + > +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ > +#define FSL_CPM_TSA_SCC2 1 > +#define FSL_CPM_TSA_SCC3 2 > +#define FSL_CPM_TSA_SCC4 3 > +#define FSL_CPM_TSA_SMC1 4 > +#define FSL_CPM_TSA_SMC2 5 > + > +#endif > -- > 2.38.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A790EC677F1 for ; Tue, 17 Jan 2023 14:56:09 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4NxBm81KlBz3cJB for ; Wed, 18 Jan 2023 01:56:08 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=209.85.160.47; helo=mail-oa1-f47.google.com; envelope-from=robherring2@gmail.com; receiver=) Received: from mail-oa1-f47.google.com (mail-oa1-f47.google.com [209.85.160.47]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4NxBlW0Cgqz3c7l for ; Wed, 18 Jan 2023 01:55:34 +1100 (AEDT) Received: by mail-oa1-f47.google.com with SMTP id 586e51a60fabf-15085b8a2f7so32210235fac.2 for ; Tue, 17 Jan 2023 06:55:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=r0xOPUwMGbHKwlz1eX+ZfzIFwn/1MAHYgP6guftK2G0=; b=AR7ynlryb4567Rp279zx6AVOrvEG9spHULmYRTDP+d5whbSSSB++T/5eatAEv1cH4V MVB/9CB/yuHEMc8+K9esR8npOhWt97D90YBa2vkbMBGOEBd6iZ8pvEmmN9qIr/Shdh1y cfaEWBf2TicrI3ls/CI6JgVh6r9TqU7StlZk8eds6q5e+e8BLIi2V+BTYBAYv4Ex29E0 IF3ko09kcXzr2i1qJUVYEB5Kysq4NQJbwUgnbXOzTYqz4J0RtI1t0ptq0XzbefO2In4U N9k9DHh7pTDTOWkmMQON2aVFnW5cbOn+y9sLOxlfOdrOyKcy7SJgo+va5Q+NJsdFatuO Xn3w== X-Gm-Message-State: AFqh2kqmkoJbr3z/xMOsc/FWvRZdZG/z1ez8nlo+oyhTOnrRall6f/lK ICKl910/nftBtaqmQX3XRQ== X-Google-Smtp-Source: AMrXdXsNUJ00dTOKvt2jfPMH4Ze0uTp6cmxdG4fza3JfdEkyhCZe9BD6Z//VMQY6JmDD12zrOOWqFg== X-Received: by 2002:a05:6870:2f02:b0:15f:3213:dfc6 with SMTP id qj2-20020a0568702f0200b0015f3213dfc6mr1901825oab.35.1673967331153; Tue, 17 Jan 2023 06:55:31 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0013ae5246449sm16348572oac.22.2023.01.17.06.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 06:55:30 -0800 (PST) Received: (nullmailer pid 3058299 invoked by uid 1000); Tue, 17 Jan 2023 14:55:29 -0000 Date: Tue, 17 Jan 2023 08:55:29 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v3 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230117145529.GA3044055-robh@kernel.org> References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230113103759.327698-2-herve.codina@bootlin.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Takashi Iwai , Liam Girdwood , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Nicholas Piggin , Krzysztof Kozlowski , Jaroslav Kysela , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. An odd line wrap length... > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++ > include/dt-bindings/soc/fsl,tsa.h | 13 + > 2 files changed, 273 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > new file mode 100644 > index 000000000000..eb17b6119abd > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > @@ -0,0 +1,260 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: | Don't need '|' if no formatting. > + The TSA is the time-slot assigner that can be found on some > + PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal > + serial controllers. Wrap at 80. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^tdm@[0-1]$': > + description: > + The TDM managed by this controller > + type: object additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 1 > + description: > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, > + Tx sync, Rx clock and Rx sync or use only two pins, > + Tx/Rx clock and Rx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four > + pins are used. With the 'fsl,common-rxtx-pins' property, > + two pins are used. > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + minItems: 2 > + maxItems: 4 > + > + fsl,mode: 'mode' is a bit vague. It's already used as well which can be a problem if there are differing types. (There's not in this case) > + $ref: /schemas/types.yaml#/definitions/string > + enum: [normal, echo, internal-loopback, control-loopback] > + default: normal > + description: | > + Operational mode: > + - normal: > + Normal operation > + - echo: > + Automatic echo. Rx data is resent on Tx > + - internal-loopback: > + The TDM transmitter is connected to the receiver. > + Data appears on Tx pin. > + - control-loopback: > + The TDM transmitter is connected to the receiver. > + The Tx pin is disconnected. > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the > + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the > + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + Data is sent on falling edge of the clock (and received on the > + rising edge). > + If 'clock-falling-edge' is not present, data is sent on the > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sample > + with e falling edge. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + fsl,tx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Tx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route to SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route to SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + fsl,rx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Rx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route from SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route from SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The destination serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + else: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + - description: External clock connected to L1TSYNC pin > + - description: External clock connected to L1TCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + - const: l1tsync > + - const: l1tclk As the names are the same, just the length varies between 2 or 4, move all this to the main definition and here just put constraints on the length. > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tsa@ae0 { > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "l1rsync", "l1rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h > new file mode 100644 > index 000000000000..2cc44e867dbe > --- /dev/null > +++ b/include/dt-bindings/soc/fsl,tsa.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H > +#define __DT_BINDINGS_SOC_FSL_TSA_H > + > +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ > +#define FSL_CPM_TSA_SCC2 1 > +#define FSL_CPM_TSA_SCC3 2 > +#define FSL_CPM_TSA_SCC4 3 > +#define FSL_CPM_TSA_SMC1 4 > +#define FSL_CPM_TSA_SMC2 5 > + > +#endif > -- > 2.38.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A0BBC63797 for ; Tue, 17 Jan 2023 14:56:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xsCIcSHT8g1oUBExW/5sE71TmDTLiD1+XAjCj4aeijA=; b=wHEpEXcG+F9uTp FvJRe/hYHj7ckYqhS1V14VUQ/uAZf83DROOsMpADhcVMmEYikHv5EjARaAlr2d/1YTcp9a/je9aB7 PRcPdk17ju252RHYimJzfT/fXALCd5N4IPrZQ/OBRLStZoxKTgphSJl/7VRphR0Y7V+9DLJmA2AZc gMfWwotmHIrfli1wywpDPer3uZeWyfIDvVK61hnzKcAoD99c2rhwFCNfdmTdp1aYCq0vZEXxwOaRl fRE4aF72vjurKV+9lvCEdRZ8ueFC+ZQUiNqeEGzYeFzJ8JxIFnmw5wN2adPssBF1SkeOmLVR9U9Sa XxgVsPbijyKfpOl76XcA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHnNC-00EgZZ-Le; Tue, 17 Jan 2023 14:55:38 +0000 Received: from mail-oa1-f52.google.com ([209.85.160.52]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pHnN8-00EgXU-8X for linux-arm-kernel@lists.infradead.org; Tue, 17 Jan 2023 14:55:37 +0000 Received: by mail-oa1-f52.google.com with SMTP id 586e51a60fabf-15eec491b40so11250857fac.12 for ; Tue, 17 Jan 2023 06:55:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=r0xOPUwMGbHKwlz1eX+ZfzIFwn/1MAHYgP6guftK2G0=; b=ttV/7K/oyT8/CBSkwnvq1ZR5C0yqh+bagJlX6PHPjxbhvnOONqZybWiI/2m2S/2gyk 99t2XO9iYCjbPKhKp0VgCi9X92AzMjcm8JmDHBozrdKygWHUAwmhh5LTIevMPCHjZsol nT78uIcc8RhBI1PwwST1N591tTAlVpwXZ7QWcXqBjD7QfYttaZkW6jKQb6+D2GZ2XZSU tA8CbNQTIlcPyZQpdRDT2QQU5m24HNpUAnfmivLhlpUTHbWizQN7LnkHEqczXmOX2VqH XNN/s4MLCZOXnJIRYFyrZHCO6FvyPXgH3+sLxGcswc/p3A7jWldOTtTxxTu4IkeLuoKx eEzA== X-Gm-Message-State: AFqh2koRmfokVRlUaGTiU8Ng9V9v/1JFP4rMetX9CI5diYjXOuK2nG48 XtU196tOWJjE+uHT7kKFqkj0s9Z7YA== X-Google-Smtp-Source: AMrXdXsNUJ00dTOKvt2jfPMH4Ze0uTp6cmxdG4fza3JfdEkyhCZe9BD6Z//VMQY6JmDD12zrOOWqFg== X-Received: by 2002:a05:6870:2f02:b0:15f:3213:dfc6 with SMTP id qj2-20020a0568702f0200b0015f3213dfc6mr1901825oab.35.1673967331153; Tue, 17 Jan 2023 06:55:31 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0013ae5246449sm16348572oac.22.2023.01.17.06.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 06:55:30 -0800 (PST) Received: (nullmailer pid 3058299 invoked by uid 1000); Tue, 17 Jan 2023 14:55:29 -0000 Date: Tue, 17 Jan 2023 08:55:29 -0600 From: Rob Herring To: Herve Codina Cc: Li Yang , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: Re: [PATCH v3 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230117145529.GA3044055-robh@kernel.org> References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230113103759.327698-2-herve.codina@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230117_065534_326175_15696B1C X-CRM114-Status: GOOD ( 33.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. An odd line wrap length... > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++ > include/dt-bindings/soc/fsl,tsa.h | 13 + > 2 files changed, 273 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > new file mode 100644 > index 000000000000..eb17b6119abd > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > @@ -0,0 +1,260 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: | Don't need '|' if no formatting. > + The TSA is the time-slot assigner that can be found on some > + PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal > + serial controllers. Wrap at 80. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^tdm@[0-1]$': > + description: > + The TDM managed by this controller > + type: object additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 1 > + description: > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, > + Tx sync, Rx clock and Rx sync or use only two pins, > + Tx/Rx clock and Rx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four > + pins are used. With the 'fsl,common-rxtx-pins' property, > + two pins are used. > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + minItems: 2 > + maxItems: 4 > + > + fsl,mode: 'mode' is a bit vague. It's already used as well which can be a problem if there are differing types. (There's not in this case) > + $ref: /schemas/types.yaml#/definitions/string > + enum: [normal, echo, internal-loopback, control-loopback] > + default: normal > + description: | > + Operational mode: > + - normal: > + Normal operation > + - echo: > + Automatic echo. Rx data is resent on Tx > + - internal-loopback: > + The TDM transmitter is connected to the receiver. > + Data appears on Tx pin. > + - control-loopback: > + The TDM transmitter is connected to the receiver. > + The Tx pin is disconnected. > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the > + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the > + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + Data is sent on falling edge of the clock (and received on the > + rising edge). > + If 'clock-falling-edge' is not present, data is sent on the > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sample > + with e falling edge. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + fsl,tx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Tx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route to SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route to SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + fsl,rx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Rx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route from SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route from SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The destination serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + else: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + - description: External clock connected to L1TSYNC pin > + - description: External clock connected to L1TCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + - const: l1tsync > + - const: l1tclk As the names are the same, just the length varies between 2 or 4, move all this to the main definition and here just put constraints on the length. > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tsa@ae0 { > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "l1rsync", "l1rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h > new file mode 100644 > index 000000000000..2cc44e867dbe > --- /dev/null > +++ b/include/dt-bindings/soc/fsl,tsa.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H > +#define __DT_BINDINGS_SOC_FSL_TSA_H > + > +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ > +#define FSL_CPM_TSA_SCC2 1 > +#define FSL_CPM_TSA_SCC3 2 > +#define FSL_CPM_TSA_SCC4 3 > +#define FSL_CPM_TSA_SMC1 4 > +#define FSL_CPM_TSA_SMC2 5 > + > +#endif > -- > 2.38.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3531C63797 for ; Tue, 17 Jan 2023 14:55:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232122AbjAQOzi (ORCPT ); Tue, 17 Jan 2023 09:55:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbjAQOze (ORCPT ); Tue, 17 Jan 2023 09:55:34 -0500 Received: from mail-oa1-f41.google.com (mail-oa1-f41.google.com [209.85.160.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 102543E62B; Tue, 17 Jan 2023 06:55:32 -0800 (PST) Received: by mail-oa1-f41.google.com with SMTP id 586e51a60fabf-15f64f2791dso1889995fac.7; Tue, 17 Jan 2023 06:55:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=r0xOPUwMGbHKwlz1eX+ZfzIFwn/1MAHYgP6guftK2G0=; b=QsmuofTh3tL6pNnLGIlkEw0QvnnBuTtu77jvG0AJmRrq3CdRtBCU0LEZ8btw0eJz7b +lzlAhyGb/1qWGKWeo+HfbzqZelrZT7QStCVepLvwk7YMACAiHsAqhWvjxembfvYG+qH 59cC+Yuhr3L7Yz1KIWN+DsgeiYgeq66fpcciMugUMYoYe6nFyAmL2CIN7RUjxwx0sRsc sYuBxaCB8IJe8HKnpjhjIXTsCYoo7Stuws3Qg/vJ7eqMcGNGE0F+lgWugrp1+Q9OJ1gX kod1mfB2IjoURiLzzTkgr0go0b0zBDc3bH8zP01uon/3AaXj6rdNuyoRZW1anmXXXo5H M2ww== X-Gm-Message-State: AFqh2krxanjSKePbknml8NCAnkReyKQkrKrO2Xg90bm19zLgmPUO+OJl TXS/6ppTpdwb321b32CfGQ== X-Google-Smtp-Source: AMrXdXsNUJ00dTOKvt2jfPMH4Ze0uTp6cmxdG4fza3JfdEkyhCZe9BD6Z//VMQY6JmDD12zrOOWqFg== X-Received: by 2002:a05:6870:2f02:b0:15f:3213:dfc6 with SMTP id qj2-20020a0568702f0200b0015f3213dfc6mr1901825oab.35.1673967331153; Tue, 17 Jan 2023 06:55:31 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0013ae5246449sm16348572oac.22.2023.01.17.06.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 06:55:30 -0800 (PST) Received: (nullmailer pid 3058299 invoked by uid 1000); Tue, 17 Jan 2023 14:55:29 -0000 Date: Tue, 17 Jan 2023 08:55:29 -0600 From: Rob Herring To: Herve Codina Cc: Li Yang , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: Re: [PATCH v3 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller Message-ID: <20230117145529.GA3044055-robh@kernel.org> References: <20230113103759.327698-1-herve.codina@bootlin.com> <20230113103759.327698-2-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230113103759.327698-2-herve.codina@bootlin.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Jan 13, 2023 at 11:37:50AM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. An odd line wrap length... > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,tsa.yaml | 260 ++++++++++++++++++ > include/dt-bindings/soc/fsl,tsa.h | 13 + > 2 files changed, 273 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > create mode 100644 include/dt-bindings/soc/fsl,tsa.h > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > new file mode 100644 > index 000000000000..eb17b6119abd > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,tsa.yaml > @@ -0,0 +1,260 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,tsa.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM Time-slot assigner (TSA) controller > + > +maintainers: > + - Herve Codina > + > +description: | Don't need '|' if no formatting. > + The TSA is the time-slot assigner that can be found on some > + PowerQUICC SoC. > + Its purpose is to route some TDM time-slots to other internal > + serial controllers. Wrap at 80. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-tsa > + - fsl,mpc866-tsa > + - const: fsl,cpm1-tsa > + > + reg: > + items: > + - description: SI (Serial Interface) register base > + - description: SI RAM base > + > + reg-names: > + items: > + - const: si_regs > + - const: si_ram > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > +patternProperties: > + '^tdm@[0-1]$': > + description: > + The TDM managed by this controller > + type: object additionalProperties: false > + > + properties: > + reg: > + minimum: 0 > + maximum: 1 > + description: > + The TDM number for this TDM, 0 for TDMa and 1 for TDMb > + > + fsl,common-rxtx-pins: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The hardware can use four dedicated pins for Tx clock, > + Tx sync, Rx clock and Rx sync or use only two pins, > + Tx/Rx clock and Rx/Rx sync. > + Without the 'fsl,common-rxtx-pins' property, the four > + pins are used. With the 'fsl,common-rxtx-pins' property, > + two pins are used. > + > + clocks: > + minItems: 2 > + maxItems: 4 > + > + clock-names: > + minItems: 2 > + maxItems: 4 > + > + fsl,mode: 'mode' is a bit vague. It's already used as well which can be a problem if there are differing types. (There's not in this case) > + $ref: /schemas/types.yaml#/definitions/string > + enum: [normal, echo, internal-loopback, control-loopback] > + default: normal > + description: | > + Operational mode: > + - normal: > + Normal operation > + - echo: > + Automatic echo. Rx data is resent on Tx > + - internal-loopback: > + The TDM transmitter is connected to the receiver. > + Data appears on Tx pin. > + - control-loopback: > + The TDM transmitter is connected to the receiver. > + The Tx pin is disconnected. > + > + fsl,rx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Receive frame sync delay in number of bits. > + Indicates the delay between the Rx sync and the first bit of the > + Rx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,tx-frame-sync-delay-bits: > + enum: [0, 1, 2, 3] > + default: 0 > + description: | > + Transmit frame sync delay in number of bits. > + Indicates the delay between the Tx sync and the first bit of the > + Tx frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. > + > + fsl,clock-falling-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + Data is sent on falling edge of the clock (and received on the > + rising edge). > + If 'clock-falling-edge' is not present, data is sent on the > + rising edge (and received on the falling edge). > + > + fsl,fsync-rising-edge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Frame sync pulses are sampled with the rising edge of the channel > + clock. If 'fsync-rising-edge' is not present, pulses are sample > + with e falling edge. > + > + fsl,double-speed-clock: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The channel clock is twice the data rate. > + > + fsl,tx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Tx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route to SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route to SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The source serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + fsl,rx-ts-routes: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + description: | > + A list of tupple that indicates the Rx time-slots routes. > + tx_ts_routes = > + < 2 0 >, /* The first 2 time slots are not used */ > + < 3 1 >, /* The next 3 ones are route from SCC2 */ > + < 4 0 >, /* The next 4 ones are not used */ > + < 2 2 >; /* The nest 2 ones are route from SCC3 */ > + items: > + items: > + - description: > + The number of time-slots > + minimum: 1 > + maximum: 64 > + - description: | > + The destination serial interface (dt-bindings/soc/fsl,tsa.h > + defines these values) > + - 0: No destination > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + - 4: SMC1 > + - 5: SMC2 > + enum: [0, 1, 2, 3, 4, 5] > + minItems: 1 > + maxItems: 64 > + > + allOf: > + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. > + # Else, the 4 clocks must be present. > + - if: > + required: > + - fsl,common-rxtx-pins > + then: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + else: > + properties: > + clocks: > + items: > + - description: External clock connected to L1RSYNC pin > + - description: External clock connected to L1RCLK pin > + - description: External clock connected to L1TSYNC pin > + - description: External clock connected to L1TCLK pin > + clock-names: > + items: > + - const: l1rsync > + - const: l1rclk > + - const: l1tsync > + - const: l1tclk As the names are the same, just the length varies between 2 or 4, move all this to the main definition and here just put constraints on the length. > + > + required: > + - reg > + - clocks > + - clock-names > + > +required: > + - compatible > + - reg > + - reg-names > + - '#address-cells' > + - '#size-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tsa@ae0 { > + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; > + reg = <0xae0 0x10>, > + <0xc00 0x200>; > + reg-names = "si_regs", "si_ram"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + tdm@0 { > + /* TDMa */ > + reg = <0>; > + > + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; > + clock-names = "l1rsync", "l1rclk"; > + > + fsl,common-rxtx-pins; > + fsl,fsync-rising-edge; > + > + fsl,tx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* TS 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + > + fsl,rx-ts-routes = < 2 0 >, /* TS 0..1 */ > + < 24 FSL_CPM_TSA_SCC4 >, /* 2..25 */ > + < 1 0 >, /* TS 26 */ > + < 5 FSL_CPM_TSA_SCC3 >; /* TS 27..31 */ > + }; > + }; > diff --git a/include/dt-bindings/soc/fsl,tsa.h b/include/dt-bindings/soc/fsl,tsa.h > new file mode 100644 > index 000000000000..2cc44e867dbe > --- /dev/null > +++ b/include/dt-bindings/soc/fsl,tsa.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > + > +#ifndef __DT_BINDINGS_SOC_FSL_TSA_H > +#define __DT_BINDINGS_SOC_FSL_TSA_H > + > +#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ > +#define FSL_CPM_TSA_SCC2 1 > +#define FSL_CPM_TSA_SCC3 2 > +#define FSL_CPM_TSA_SCC4 3 > +#define FSL_CPM_TSA_SMC1 4 > +#define FSL_CPM_TSA_SMC2 5 > + > +#endif > -- > 2.38.1 >