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From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v3 3/4] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
Date: Fri, 20 Jan 2023 18:29:49 +0530	[thread overview]
Message-ID: <20230120125950.2246378-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com>

The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/time_helper.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 4fb2a471a9..b654f91af9 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -72,6 +72,30 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
         riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
     }
 
+    /*
+     * Sstc specification says the following about timer interrupt:
+     * "A supervisor timer interrupt becomes pending - as reflected in
+     * the STIP bit in the mip and sip registers - whenever time contains
+     * a value greater than or equal to stimecmp, treating the values
+     * as unsigned integers. Writes to stimecmp are guaranteed to be
+     * reflected in STIP eventually, but not necessarily immediately.
+     * The interrupt remains posted until stimecmp becomes greater
+     * than time - typically as a result of writing stimecmp."
+     *
+     * When timecmp = UINT64_MAX, the time CSR will eventually reach
+     * timecmp value but on next timer tick the time CSR will wrap-around
+     * and become zero which is less than UINT64_MAX. Now, the timer
+     * interrupt behaves like a level triggered interrupt so it will
+     * become 1 when time = timecmp = UINT64_MAX and next timer tick
+     * it will become 0 again because time = 0 < timecmp = UINT64_MAX.
+     *
+     * Based on above, we don't re-start the QEMU timer when timecmp
+     * equals UINT64_MAX.
+     */
+    if (timecmp == UINT64_MAX) {
+        return;
+    }
+
     /* otherwise, set up the future timer interrupt */
     diff = timecmp - rtc_r;
     /* back to ns (note args switched in muldiv64) */
-- 
2.34.1



  parent reply	other threads:[~2023-01-20 13:00 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-20 12:59 [PATCH v3 0/4] Nested virtualization fixes for QEMU Anup Patel
2023-01-20 12:59 ` [PATCH v3 1/4] target/riscv: Update VS timer whenever htimedelta changes Anup Patel
2023-01-20 12:59 ` [PATCH v3 2/4] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Anup Patel
2023-01-20 12:59 ` Anup Patel [this message]
2023-01-20 12:59 ` [PATCH v3 4/4] target/riscv: Ensure opcode is saved for all relevant instructions Anup Patel
2023-01-24  0:00   ` Alistair Francis
2023-01-24  0:58 ` [PATCH v3 0/4] Nested virtualization fixes for QEMU Alistair Francis

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