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From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: [PATCH v3 4/5] hw/char/pl011: better handling of FIFO flags on LCR reset
Date: Fri, 20 Jan 2023 16:54:46 +0100	[thread overview]
Message-ID: <20230120155447.31702-5-eiakovlev@linux.microsoft.com> (raw)
In-Reply-To: <20230120155447.31702-1-eiakovlev@linux.microsoft.com>

Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
---
 hw/char/pl011.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index f9413f3703..c72fbb7d50 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 }
 
+static inline void pl011_reset_fifo(PL011State *s)
+{
+    s->read_count = 0;
+    s->read_pos = 0;
+
+    /* Reset FIFO flags */
+    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
+    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset,
     case 11: /* UARTLCR_H */
         /* Reset the FIFO state on FIFO enable or disable */
         if ((s->lcr ^ value) & 0x10) {
-            s->read_count = 0;
-            s->read_pos = 0;
+            pl011_reset_fifo(s);
         }
         if ((s->lcr ^ value) & 0x1) {
             int break_enable = value & 0x1;
@@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev)
     s->ilpr = 0;
     s->ibrd = 0;
     s->fbrd = 0;
-    s->read_pos = 0;
-    s->read_count = 0;
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
-    s->flags = 0x90;
+    s->flags = 0;
+    pl011_reset_fifo(s);
 }
 
 static void pl011_class_init(ObjectClass *oc, void *data)
-- 
2.34.1


  parent reply	other threads:[~2023-01-20 15:55 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-20 15:54 [PATCH v3 0/5] Series of fixes for PL011 char device Evgeny Iakovlev
2023-01-20 15:54 ` [PATCH v3 1/5] hw/char/pl011: refactor FIFO depth handling code Evgeny Iakovlev
2023-01-20 18:23   ` Peter Maydell
2023-01-23  7:29   ` Philippe Mathieu-Daudé
2023-01-20 15:54 ` [PATCH v3 2/5] hw/char/pl011: add post_load hook for backwards-compatibility Evgeny Iakovlev
2023-01-20 18:22   ` Peter Maydell
2023-01-23 14:39     ` Evgeny Iakovlev
2023-01-20 15:54 ` [PATCH v3 3/5] hw/char/pl011: implement a reset method Evgeny Iakovlev
2023-01-20 18:23   ` Peter Maydell
2023-01-23  7:25   ` Philippe Mathieu-Daudé
2023-01-20 15:54 ` Evgeny Iakovlev [this message]
2023-01-20 18:23   ` [PATCH v3 4/5] hw/char/pl011: better handling of FIFO flags on LCR reset Peter Maydell
2023-01-20 15:54 ` [PATCH v3 5/5] hw/char/pl011: check if UART is enabled before RX or TX operation Evgeny Iakovlev
2023-01-23  8:14   ` Philippe Mathieu-Daudé
2023-01-23 14:43     ` Evgeny Iakovlev
2023-01-23 15:21       ` Philippe Mathieu-Daudé
2023-01-23 15:59         ` Evgeny Iakovlev
2023-01-23 16:09           ` Evgeny Iakovlev
2023-01-23 16:45             ` Philippe Mathieu-Daudé
2023-01-23 16:23         ` Peter Maydell
2023-01-23 16:41           ` Philippe Mathieu-Daudé
2023-01-25 14:50             ` Evgeny Iakovlev

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