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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w17-20020a056870e2d100b00144e6ffe9e5sm5534767oad.47.2023.01.30.10.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:30:38 -0800 (PST) Received: (nullmailer pid 3079408 invoked by uid 1000); Mon, 30 Jan 2023 18:30:37 -0000 Date: Mon, 30 Jan 2023 12:30:37 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v4 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Message-ID: <20230130183037.GA3076426-robh@kernel.org> References: <20230126083222.374243-1-herve.codina@bootlin.com> <20230126083222.374243-6-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230126083222.374243-6-herve.codina@bootlin.com> X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Michael Ellerman , Takashi Iwai , Liam Girdwood , Christophe Leroy , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Nicholas Piggin , Krzysztof Kozlowski , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Thu, Jan 26, 2023 at 09:32:17AM +0100, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++ fsl,cpm1-scc-qmc.yaml > 1 file changed, 167 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..9141a8ca183b > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,167 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina > + > +description: > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one > + serial controller using the same TDM physical interface routed from TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa-serial: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TSA node > + - enum: [1, 2, 3] > + description: | > + TSA serial interface (dt-bindings/soc/fsl,tsa.h defines these > + values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + description: > + Should be a phandle/number pair. The phandle to TSA node and the TSA > + serial interface to use. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 What's this? > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,operational-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: | > + The channel operational mode > + - hdlc: The channel handles HDLC frames > + - transparent: The channel handles raw data without any processing > + > + fsl,reverse-data: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The bit order as seen on the channels is reversed, > + transmitting/receiving the MSB of each octet first. > + This flag is used only in 'transparent' mode. > + > + fsl,tx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Tx time-slots within the Tx time-slots routed by the > + TSA to this cell. > + > + fsl,rx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Rx time-slots within the Rx time-slots routed by the > + TSA to this cell. > + > + required: > + - reg > + - fsl,tx-ts-mask > + - fsl,rx-ts-mask > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - fsl,tsa-serial > + - '#address-cells' > + - '#size-cells' > + - '#chan-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + qmc@a60 { > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; > + reg = <0xa60 0x20>, > + <0x3f00 0xc0>, > + <0x2000 0x1000>; > + reg-names = "scc_regs", "scc_pram", "dpram"; > + interrupts = <27>; > + interrupt-parent = <&CPM_PIC>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #chan-cells = <1>; > + > + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; > + > + channel@16 { > + /* Ch16 : First 4 even TS from all routed from TSA */ > + reg = <16>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x000000aa>; > + fsl,rx-ts-mask = <0x00000000 0x000000aa>; > + }; > + > + channel@17 { > + /* Ch17 : First 4 odd TS from all routed from TSA */ > + reg = <17>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x00000055>; > + fsl,rx-ts-mask = <0x00000000 0x00000055>; > + }; > + > + channel@19 { > + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ > + reg = <19>; > + fsl,mode = "hdlc"; > + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; > + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; > + }; > + }; > -- > 2.39.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D4C6C54EAA for ; Mon, 30 Jan 2023 18:31:14 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4P5GwJ2Rcmz3f4X for ; Tue, 31 Jan 2023 05:31:12 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=209.85.160.44; helo=mail-oa1-f44.google.com; envelope-from=robherring2@gmail.com; receiver=) Received: from mail-oa1-f44.google.com (mail-oa1-f44.google.com [209.85.160.44]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4P5Gvj5bVYz3bZv for ; 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w17-20020a056870e2d100b00144e6ffe9e5sm5534767oad.47.2023.01.30.10.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:30:38 -0800 (PST) Received: (nullmailer pid 3079408 invoked by uid 1000); Mon, 30 Jan 2023 18:30:37 -0000 Date: Mon, 30 Jan 2023 12:30:37 -0600 From: Rob Herring To: Herve Codina Subject: Re: [PATCH v4 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Message-ID: <20230130183037.GA3076426-robh@kernel.org> References: <20230126083222.374243-1-herve.codina@bootlin.com> <20230126083222.374243-6-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230126083222.374243-6-herve.codina@bootlin.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Fabio Estevam , linux-kernel@vger.kernel.org, Thomas Petazzoni , Xiubo Li , Takashi Iwai , Liam Girdwood , Li Yang , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, Mark Brown , Nicholas Piggin , Krzysztof Kozlowski , Jaroslav Kysela , Shengjiu Wang , linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jan 26, 2023 at 09:32:17AM +0100, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++ fsl,cpm1-scc-qmc.yaml > 1 file changed, 167 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..9141a8ca183b > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,167 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina > + > +description: > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one > + serial controller using the same TDM physical interface routed from TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa-serial: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TSA node > + - enum: [1, 2, 3] > + description: | > + TSA serial interface (dt-bindings/soc/fsl,tsa.h defines these > + values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + description: > + Should be a phandle/number pair. The phandle to TSA node and the TSA > + serial interface to use. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 What's this? > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,operational-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: | > + The channel operational mode > + - hdlc: The channel handles HDLC frames > + - transparent: The channel handles raw data without any processing > + > + fsl,reverse-data: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The bit order as seen on the channels is reversed, > + transmitting/receiving the MSB of each octet first. > + This flag is used only in 'transparent' mode. > + > + fsl,tx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Tx time-slots within the Tx time-slots routed by the > + TSA to this cell. > + > + fsl,rx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Rx time-slots within the Rx time-slots routed by the > + TSA to this cell. > + > + required: > + - reg > + - fsl,tx-ts-mask > + - fsl,rx-ts-mask > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - fsl,tsa-serial > + - '#address-cells' > + - '#size-cells' > + - '#chan-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + qmc@a60 { > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; > + reg = <0xa60 0x20>, > + <0x3f00 0xc0>, > + <0x2000 0x1000>; > + reg-names = "scc_regs", "scc_pram", "dpram"; > + interrupts = <27>; > + interrupt-parent = <&CPM_PIC>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #chan-cells = <1>; > + > + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; > + > + channel@16 { > + /* Ch16 : First 4 even TS from all routed from TSA */ > + reg = <16>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x000000aa>; > + fsl,rx-ts-mask = <0x00000000 0x000000aa>; > + }; > + > + channel@17 { > + /* Ch17 : First 4 odd TS from all routed from TSA */ > + reg = <17>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x00000055>; > + fsl,rx-ts-mask = <0x00000000 0x00000055>; > + }; > + > + channel@19 { > + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ > + reg = <19>; > + fsl,mode = "hdlc"; > + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; > + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; > + }; > + }; > -- > 2.39.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3DDCC61D97 for ; Mon, 30 Jan 2023 18:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ynfTjpiGCTofgGsHM/u67pT/wrfk5t5YY9mzaxEUROc=; b=kGEu7kYYGatFbj fkTn+DWVu4eUEm7mjis17GJJNWYXbit5ud7kqLa210Wmje2m8LHHGqckVzlNESUofWi+TcpHPkc9T kUgXt+WBUdUcuJrYmPmJBFWOs/TrKIltX1IRa32sn9N2D616VO+y4ZzPgDx94NzWdLXxqpGdnZOUZ KaCJI+li1YPF3FBoFOjUVi5++29lQsxDV0Dn4kRMiyFgLAoCmtXN5Iyeso2TI3wkMU3+Fh1kryACC w5h2o3ZWVCYYMT7lhvVZQdnvpC4+fDKweKnjl8IJwuLH8HjgiJ+OIOOIUN9DMHJYl8KMdDI7nmfWY q0T/aDYaU+Vkt5bEm38w==; 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w17-20020a056870e2d100b00144e6ffe9e5sm5534767oad.47.2023.01.30.10.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:30:38 -0800 (PST) Received: (nullmailer pid 3079408 invoked by uid 1000); Mon, 30 Jan 2023 18:30:37 -0000 Date: Mon, 30 Jan 2023 12:30:37 -0600 From: Rob Herring To: Herve Codina Cc: Li Yang , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: Re: [PATCH v4 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Message-ID: <20230130183037.GA3076426-robh@kernel.org> References: <20230126083222.374243-1-herve.codina@bootlin.com> <20230126083222.374243-6-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230126083222.374243-6-herve.codina@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230130_103041_647246_5A23FAE3 X-CRM114-Status: GOOD ( 25.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 26, 2023 at 09:32:17AM +0100, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++ fsl,cpm1-scc-qmc.yaml > 1 file changed, 167 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..9141a8ca183b > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,167 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina > + > +description: > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one > + serial controller using the same TDM physical interface routed from TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa-serial: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TSA node > + - enum: [1, 2, 3] > + description: | > + TSA serial interface (dt-bindings/soc/fsl,tsa.h defines these > + values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + description: > + Should be a phandle/number pair. The phandle to TSA node and the TSA > + serial interface to use. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 What's this? > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,operational-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: | > + The channel operational mode > + - hdlc: The channel handles HDLC frames > + - transparent: The channel handles raw data without any processing > + > + fsl,reverse-data: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The bit order as seen on the channels is reversed, > + transmitting/receiving the MSB of each octet first. > + This flag is used only in 'transparent' mode. > + > + fsl,tx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Tx time-slots within the Tx time-slots routed by the > + TSA to this cell. > + > + fsl,rx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Rx time-slots within the Rx time-slots routed by the > + TSA to this cell. > + > + required: > + - reg > + - fsl,tx-ts-mask > + - fsl,rx-ts-mask > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - fsl,tsa-serial > + - '#address-cells' > + - '#size-cells' > + - '#chan-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + qmc@a60 { > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; > + reg = <0xa60 0x20>, > + <0x3f00 0xc0>, > + <0x2000 0x1000>; > + reg-names = "scc_regs", "scc_pram", "dpram"; > + interrupts = <27>; > + interrupt-parent = <&CPM_PIC>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #chan-cells = <1>; > + > + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; > + > + channel@16 { > + /* Ch16 : First 4 even TS from all routed from TSA */ > + reg = <16>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x000000aa>; > + fsl,rx-ts-mask = <0x00000000 0x000000aa>; > + }; > + > + channel@17 { > + /* Ch17 : First 4 odd TS from all routed from TSA */ > + reg = <17>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x00000055>; > + fsl,rx-ts-mask = <0x00000000 0x00000055>; > + }; > + > + channel@19 { > + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ > + reg = <19>; > + fsl,mode = "hdlc"; > + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; > + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; > + }; > + }; > -- > 2.39.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A5BBC636CB for ; Mon, 30 Jan 2023 18:31:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238180AbjA3Sby (ORCPT ); Mon, 30 Jan 2023 13:31:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238164AbjA3Sb1 (ORCPT ); Mon, 30 Jan 2023 13:31:27 -0500 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15C454614A; 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w17-20020a056870e2d100b00144e6ffe9e5sm5534767oad.47.2023.01.30.10.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 10:30:38 -0800 (PST) Received: (nullmailer pid 3079408 invoked by uid 1000); Mon, 30 Jan 2023 18:30:37 -0000 Date: Mon, 30 Jan 2023 12:30:37 -0600 From: Rob Herring To: Herve Codina Cc: Li Yang , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Christophe Leroy , Michael Ellerman , Nicholas Piggin , Qiang Zhao , Jaroslav Kysela , Takashi Iwai , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: Re: [PATCH v4 05/10] dt-bindings: soc: fsl: cpm_qe: Add QMC controller Message-ID: <20230130183037.GA3076426-robh@kernel.org> References: <20230126083222.374243-1-herve.codina@bootlin.com> <20230126083222.374243-6-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230126083222.374243-6-herve.codina@bootlin.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jan 26, 2023 at 09:32:17AM +0100, Herve Codina wrote: > Add support for the QMC (QUICC Multichannel Controller) > available in some PowerQUICC SoC such as MPC885 or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,qmc.yaml | 167 ++++++++++++++++++ fsl,cpm1-scc-qmc.yaml > 1 file changed, 167 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > > diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > new file mode 100644 > index 000000000000..9141a8ca183b > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qmc.yaml > @@ -0,0 +1,167 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qmc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PowerQUICC CPM QUICC Multichannel Controller (QMC) > + > +maintainers: > + - Herve Codina > + > +description: > + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one > + serial controller using the same TDM physical interface routed from TSA. > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,mpc885-scc-qmc > + - fsl,mpc866-scc-qmc > + - const: fsl,cpm1-scc-qmc > + > + reg: > + items: > + - description: SCC (Serial communication controller) register base > + - description: SCC parameter ram base > + - description: Dual port ram base > + > + reg-names: > + items: > + - const: scc_regs > + - const: scc_pram > + - const: dpram > + > + interrupts: > + maxItems: 1 > + description: SCC interrupt line in the CPM interrupt controller > + > + fsl,tsa-serial: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to TSA node > + - enum: [1, 2, 3] > + description: | > + TSA serial interface (dt-bindings/soc/fsl,tsa.h defines these > + values) > + - 1: SCC2 > + - 2: SCC3 > + - 3: SCC4 > + description: > + Should be a phandle/number pair. The phandle to TSA node and the TSA > + serial interface to use. > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#chan-cells': > + const: 1 What's this? > + > +patternProperties: > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': > + description: > + A channel managed by this controller > + type: object > + > + properties: > + reg: > + minimum: 0 > + maximum: 63 > + description: > + The channel number > + > + fsl,operational-mode: > + $ref: /schemas/types.yaml#/definitions/string > + enum: [transparent, hdlc] > + default: transparent > + description: | > + The channel operational mode > + - hdlc: The channel handles HDLC frames > + - transparent: The channel handles raw data without any processing > + > + fsl,reverse-data: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + The bit order as seen on the channels is reversed, > + transmitting/receiving the MSB of each octet first. > + This flag is used only in 'transparent' mode. > + > + fsl,tx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Tx time-slots within the Tx time-slots routed by the > + TSA to this cell. > + > + fsl,rx-ts-mask: > + $ref: /schemas/types.yaml#/definitions/uint64 > + description: > + Channel assigned Rx time-slots within the Rx time-slots routed by the > + TSA to this cell. > + > + required: > + - reg > + - fsl,tx-ts-mask > + - fsl,rx-ts-mask > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - fsl,tsa-serial > + - '#address-cells' > + - '#size-cells' > + - '#chan-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + qmc@a60 { > + compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; > + reg = <0xa60 0x20>, > + <0x3f00 0xc0>, > + <0x2000 0x1000>; > + reg-names = "scc_regs", "scc_pram", "dpram"; > + interrupts = <27>; > + interrupt-parent = <&CPM_PIC>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + #chan-cells = <1>; > + > + fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; > + > + channel@16 { > + /* Ch16 : First 4 even TS from all routed from TSA */ > + reg = <16>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x000000aa>; > + fsl,rx-ts-mask = <0x00000000 0x000000aa>; > + }; > + > + channel@17 { > + /* Ch17 : First 4 odd TS from all routed from TSA */ > + reg = <17>; > + fsl,mode = "transparent"; > + fsl,reverse-data; > + fsl,tx-ts-mask = <0x00000000 0x00000055>; > + fsl,rx-ts-mask = <0x00000000 0x00000055>; > + }; > + > + channel@19 { > + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ > + reg = <19>; > + fsl,mode = "hdlc"; > + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; > + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; > + }; > + }; > -- > 2.39.0 >