From: Shashank Sharma <shashank.sharma@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: alexander.deucher@amd.com, christian.koenig@amd.com,
shashank.sharma@amd.com
Subject: [PATCH 06/13] drm/amdgpu: rename gmc.aper_base/size
Date: Fri, 3 Feb 2023 20:08:23 +0100 [thread overview]
Message-ID: <20230203190836.1987-7-shashank.sharma@amd.com> (raw)
In-Reply-To: <20230203190836.1987-1-shashank.sharma@amd.com>
From: Alex Deucher <alexander.deucher@amd.com>
This patch renames aper_base and aper_size parameters (in adev->gmc),
to vram_aper_base and vram_aper_size, to differentiate it from the
doorbell BAR.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_bar_mgr.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++--
14 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index f99d4873bf22..58689b2a2d1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -438,7 +438,7 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
mem_info->vram_width = adev->gmc.vram_width;
pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
- &adev->gmc.aper_base,
+ &adev->gmc.vram_aper_base,
mem_info->local_mem_size_public,
mem_info->local_mem_size_private);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bar_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bar_mgr.c
index 0e0f212bd71c..3257da5c3a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bar_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bar_mgr.c
@@ -701,7 +701,7 @@ int amdgpu_bar_mgr_alloc_sgt(struct amdgpu_device *adev,
*/
amdgpu_res_first(res, offset, length, &cursor);
for_each_sgtable_sg((*sgt), sg, i) {
- phys_addr_t phys = cursor.start + adev->gmc.aper_base;
+ phys_addr_t phys = cursor.start + adev->gmc.vram_aper_base;
size_t size = cursor.size;
dma_addr_t addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0b6a394e109b..45588b7919fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3961,7 +3961,7 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
/* Memory manager related */
if (!adev->gmc.xgmi.connected_to_cpu) {
arch_phys_wc_del(adev->gmc.vram_mtrr);
- arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+ arch_io_free_memtype_wc(adev->gmc.vram_aper_base, adev->gmc.vram_aper_size);
}
}
@@ -5562,14 +5562,14 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
uint64_t address_mask = peer_adev->dev->dma_mask ?
~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
resource_size_t aper_limit =
- adev->gmc.aper_base + adev->gmc.aper_size - 1;
+ adev->gmc.vram_aper_base + adev->gmc.vram_aper_size - 1;
bool p2p_access =
!adev->gmc.xgmi.connected_to_cpu &&
!(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
- !(adev->gmc.aper_base & address_mask ||
+ !(adev->gmc.vram_aper_base & address_mask ||
aper_limit & address_mask));
#else
return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 02a4c93673ce..c7e64e234de6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -775,7 +775,7 @@ uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
*/
uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
{
- return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
+ return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.vram_aper_base;
}
int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 0305b660cd17..bb7076ecbf01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -167,8 +167,8 @@ struct amdgpu_gmc {
* gart/vram_start/end field as the later is from
* GPU's view and aper_base is from CPU's view.
*/
- resource_size_t aper_size;
- resource_size_t aper_base;
+ resource_size_t vram_aper_size;
+ resource_size_t vram_aper_base;
/* for some chips with <= 32MB we need to lie
* about vram size near mc fb location */
u64 mc_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ca85d64a72c2..887fc53a7d16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1046,8 +1046,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
/* On A+A platform, VRAM can be mapped as WB */
if (!adev->gmc.xgmi.connected_to_cpu) {
/* reserve PAT memory space to WC for VRAM */
- int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
- adev->gmc.aper_size);
+ int r = arch_io_reserve_memtype_wc(adev->gmc.vram_aper_base,
+ adev->gmc.vram_aper_size);
if (r) {
DRM_ERROR("Unable to set WC memtype for the aperture base\n");
@@ -1055,13 +1055,13 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
}
/* Add an MTRR for the VRAM */
- adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
- adev->gmc.aper_size);
+ adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.vram_aper_base,
+ adev->gmc.vram_aper_size);
}
DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
adev->gmc.mc_vram_size >> 20,
- (unsigned long long)adev->gmc.aper_size >> 20);
+ (unsigned long long)adev->gmc.vram_aper_size >> 20);
DRM_INFO("RAM width %dbits %s\n",
adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
return amdgpu_ttm_init(adev);
@@ -1083,7 +1083,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
if (!adev->gmc.xgmi.connected_to_cpu) {
arch_phys_wc_del(adev->gmc.vram_mtrr);
- arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
+ arch_io_free_memtype_wc(adev->gmc.vram_aper_base, adev->gmc.vram_aper_size);
}
drm_dev_exit(idx);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 196ba62ef721..bb2230d14ea6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -583,7 +583,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
mem->bus.addr = (u8 *)adev->mman.vram_aper_base_kaddr +
mem->bus.offset;
- mem->bus.offset += adev->gmc.aper_base;
+ mem->bus.offset += adev->gmc.vram_aper_base;
mem->bus.is_iomem = true;
break;
default:
@@ -600,7 +600,7 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
&cursor);
- return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
+ return (adev->gmc.vram_aper_base + cursor.start) >> PAGE_SHIFT;
}
/**
@@ -1752,12 +1752,12 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
#ifdef CONFIG_64BIT
#ifdef CONFIG_X86
if (adev->gmc.xgmi.connected_to_cpu)
- adev->mman.vram_aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
+ adev->mman.vram_aper_base_kaddr = ioremap_cache(adev->gmc.vram_aper_base,
adev->gmc.visible_vram_size);
else
#endif
- adev->mman.vram_aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
+ adev->mman.vram_aper_base_kaddr = ioremap_wc(adev->gmc.vram_aper_base,
adev->gmc.visible_vram_size);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 21e46817d82d..b2e4f4f06bdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -825,18 +825,18 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
#ifdef CONFIG_X86_64
if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
- adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
- adev->gmc.aper_size = adev->gmc.real_vram_size;
+ adev->gmc.vram_aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
+ adev->gmc.vram_aper_size = adev->gmc.real_vram_size;
}
#endif
/* In case the PCI BAR is larger than the actual amount of vram */
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 4326078689cd..f993ce264c3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -692,17 +692,17 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
#ifdef CONFIG_X86_64
if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
- adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
- adev->gmc.aper_size = adev->gmc.real_vram_size;
+ adev->gmc.vram_aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
+ adev->gmc.vram_aper_size = adev->gmc.real_vram_size;
}
#endif
/* In case the PCI BAR is larger than the actual amount of vram */
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index ec291d28edff..cd159309e9e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -324,9 +324,9 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
/* set the gart size */
if (amdgpu_gart_size == -1) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 979da6f510e8..8ee9731a0c8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -377,20 +377,20 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
#ifdef CONFIG_X86_64
if ((adev->flags & AMD_IS_APU) &&
- adev->gmc.real_vram_size > adev->gmc.aper_size &&
+ adev->gmc.real_vram_size > adev->gmc.vram_aper_size &&
!amdgpu_passthrough(adev)) {
- adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
- adev->gmc.aper_size = adev->gmc.real_vram_size;
+ adev->gmc.vram_aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
+ adev->gmc.vram_aper_size = adev->gmc.real_vram_size;
}
#endif
/* In case the PCI BAR is larger than the actual amount of vram */
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 382dde1ce74c..259d797358f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -577,18 +577,18 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
#ifdef CONFIG_X86_64
if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
- adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
- adev->gmc.aper_size = adev->gmc.real_vram_size;
+ adev->gmc.vram_aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
+ adev->gmc.vram_aper_size = adev->gmc.real_vram_size;
}
#endif
/* In case the PCI BAR is larger than the actual amount of vram */
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 08d6cf79fb15..a7074995d97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1509,8 +1509,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (r)
return r;
}
- adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
- adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+ adev->gmc.vram_aper_base = pci_resource_start(adev->pdev, 0);
+ adev->gmc.vram_aper_size = pci_resource_len(adev->pdev, 0);
#ifdef CONFIG_X86_64
/*
@@ -1528,16 +1528,16 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
(adev->gmc.xgmi.supported &&
adev->gmc.xgmi.connected_to_cpu)) {
- adev->gmc.aper_base =
+ adev->gmc.vram_aper_base =
adev->gfxhub.funcs->get_mc_fb_offset(adev) +
adev->gmc.xgmi.physical_node_id *
adev->gmc.xgmi.node_segment_size;
- adev->gmc.aper_size = adev->gmc.real_vram_size;
+ adev->gmc.vram_aper_size = adev->gmc.real_vram_size;
}
#endif
/* In case the PCI BAR is larger than the actual amount of vram */
- adev->gmc.visible_vram_size = adev->gmc.aper_size;
+ adev->gmc.visible_vram_size = adev->gmc.vram_aper_size;
if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 10048ce16aea..c86c6705b470 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -1002,8 +1002,8 @@ int svm_migrate_init(struct amdgpu_device *adev)
*/
size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20);
if (adev->gmc.xgmi.connected_to_cpu) {
- pgmap->range.start = adev->gmc.aper_base;
- pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1;
+ pgmap->range.start = adev->gmc.vram_aper_base;
+ pgmap->range.end = adev->gmc.vram_aper_base + adev->gmc.vram_aper_size - 1;
pgmap->type = MEMORY_DEVICE_COHERENT;
} else {
res = devm_request_free_mem_region(adev->dev, &iomem_resource, size);
--
2.34.1
next prev parent reply other threads:[~2023-02-03 19:09 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 19:08 [PATCH 00/13] Re-design doorbell framework for usermode queues Shashank Sharma
2023-02-03 19:08 ` [PATCH 01/13] drm/amdgpu: add UAPI for allocating doorbell memory Shashank Sharma
2023-02-06 11:19 ` Christian König
2023-02-06 15:31 ` Shashank Sharma
2023-02-03 19:08 ` [PATCH 02/13] drm/amdgpu: rename vram_mgr functions to bar_mgr Shashank Sharma
2023-02-06 11:20 ` Christian König
2023-02-06 15:34 ` Shashank Sharma
2023-02-06 16:03 ` Christian König
2023-02-06 16:17 ` Alex Deucher
2023-02-03 19:08 ` [PATCH 03/13] drm/amdgpu: rename amdgpu_vram_mgr.c/h to amdgpu_bar_mgr.c/h Shashank Sharma
2023-02-03 19:08 ` [PATCH 04/13] drm/amdgpu: replace aper_base_kaddr with vram_aper_base_kaddr Shashank Sharma
2023-02-06 11:21 ` Christian König
2023-02-03 19:08 ` [PATCH 05/13] drm/amdgpu: add doorbell support to amdgpu_bar_mgr Shashank Sharma
2023-02-03 19:08 ` Shashank Sharma [this message]
2023-02-06 11:22 ` [PATCH 06/13] drm/amdgpu: rename gmc.aper_base/size Christian König
2023-02-03 19:08 ` [PATCH 07/13] drm/amdgpu: store doorbell info in gmc structure Shashank Sharma
2023-02-06 11:23 ` Christian König
2023-02-03 19:08 ` [PATCH 08/13] drm/amdgpu: move doorbell ptr into mman structure Shashank Sharma
2023-02-06 11:24 ` Christian König
2023-02-03 19:08 ` [PATCH 09/13] drm/amdgpu: accommodate DOMAIN/PL_DOORBELL Shashank Sharma
2023-02-06 11:30 ` Christian König
2023-02-06 16:30 ` Alex Deucher
2023-02-03 19:08 ` [PATCH 09/14] drm/amdgpu: move doorbell aperture handling into ttm_init Shashank Sharma
2023-02-06 16:20 ` Christian König
2023-02-03 19:08 ` [PATCH 10/14] drm/amdgpu: accommodate DOMAIN/PL_DOORBELL Shashank Sharma
2023-02-03 19:08 ` [PATCH 10/13] drm/amdgpu: doorbell support in get_memory functions Shashank Sharma
2023-02-06 16:30 ` Christian König
2023-02-03 19:08 ` [PATCH 11/14] " Shashank Sharma
2023-02-03 19:08 ` [PATCH 11/13] drm/amdgpu: initialize doorbell memory pool Shashank Sharma
2023-02-03 19:08 ` [PATCH 12/13] drm/amdgpu: add domain info in bo_create_kernel_at Shashank Sharma
2023-02-06 16:51 ` Christian König
2023-02-06 17:01 ` Alex Deucher
2023-02-06 17:03 ` Christian König
2023-02-03 19:08 ` [PATCH 12/14] drm/amdgpu: initialize doorbell memory pool Shashank Sharma
2023-02-06 16:54 ` Christian König
2023-02-03 19:08 ` [PATCH 13/14] drm/amdgpu: add domain info in bo_create_kernel_at Shashank Sharma
2023-02-03 19:08 ` [PATCH 13/13] drm/amdgpu: introduce doorbell bo in kernel Shashank Sharma
2023-02-03 19:08 ` [PATCH 14/14] " Shashank Sharma
2023-02-06 16:57 ` Christian König
2023-02-06 17:19 ` Shashank Sharma
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230203190836.1987-7-shashank.sharma@amd.com \
--to=shashank.sharma@amd.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=christian.koenig@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.