From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pSh15-0000EZ-Vl for mharc-qemu-riscv@gnu.org; Thu, 16 Feb 2023 11:21:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSh14-0000Cl-QZ for qemu-riscv@nongnu.org; Thu, 16 Feb 2023 11:21:50 -0500 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSh13-0006AI-6D for qemu-riscv@nongnu.org; Thu, 16 Feb 2023 11:21:50 -0500 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-16e809949eeso1564435fac.9 for ; Thu, 16 Feb 2023 08:21:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wh23YR+MTb3Z95gd9Zx/XoNgfzFVu0diZGWAULwkKw8=; b=JuWAG+rBxbZq8ALDs2bOjCg/CQc+V4Vbk/LYNIl1/9I33PVTQccjQGJbdjsDqLP6z7 9+BhMjXMYctJrk6CuVx6Xdmm7WoU4g8nqTxvR8RD5SBn89OCLsvJwOzPkmniXB3OzoGS JfrLS8V/ZWAZUszBCK+YN1glv+t4em856tsJcrGBEr3I2mtUJmW8FPFrSqj/7bXTQ96O AOe3absJXizGdojiCcQHT+/h0qYloVYNjuZQIKXQc6gFvD8kWgk6Us8tMgNA0PVIJXja LarKGGF/+Loh9Ivwgc5F2lSbWimArORfL4x4S21iSG6TcNPlFnfKmqaUh7R/gEbCc9DE YHeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wh23YR+MTb3Z95gd9Zx/XoNgfzFVu0diZGWAULwkKw8=; b=RHSfCTfvnGUQjTBq2BzFCi+kiBlbffsSb6qTAMti3KfP6znLjkV5EM3MZnttZNw/xp aMvGSB+nDvIc9ddEjSwe/AbNHvei8PaDz40KZEGtH86DYAwXrhq6yqSekL7BI2dwvJec 8kFFqqAwaZXSCQ93MjIbifPvObCvleZjFF4xdkRQfmDpqEge5uea0V+SBfj9QDe9UU94 73fJVKeV55nQCWWCM7z9PXNNgn2cobRa2xZ4OtS0DMAlJf40yMHAZIBhVsRyu8w2W4UQ 5x3ONtQPtmuzDWC9OwUFWNb4n9CW5nT85Me3QKHGraKArbz1RHVn63ZMIEj8e/Z+kUKF 5M1w== X-Gm-Message-State: AO0yUKWKarqkizwUMgeknOg0UGu4M41fD1Q3Nxw0jAXbtZl1AvveT8AX ZLfXxC2mGjvVuAezjI0efeMNJQ== X-Google-Smtp-Source: AK7set9LCztqzTCDFdsS0sUH+je/2JKKaZ39kvRfDmk0cei4WjSD1t0X3I7dk6P2XU3OIQovdtnoCg== X-Received: by 2002:a05:6870:a44c:b0:161:239b:5a92 with SMTP id n12-20020a056870a44c00b00161239b5a92mr1331122oal.13.1676564507135; Thu, 16 Feb 2023 08:21:47 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id z17-20020a056870e15100b001600797d1b5sm693029oaa.41.2023.02.16.08.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 08:21:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v5 5/9] target/riscv: remove RISCV_FEATURE_EPMP Date: Thu, 16 Feb 2023 13:21:22 -0300 Message-Id: <20230216162126.809482-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230216162126.809482-1-dbarboza@ventanamicro.com> References: <20230216162126.809482-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Feb 2023 16:21:51 -0000 RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 10 +++------- target/riscv/cpu.h | 1 - target/riscv/csr.c | 2 +- target/riscv/pmp.c | 4 ++-- 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4585ca74dc..71b2042d73 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_PMP); } - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); - + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - if (!cpu->cfg.pmp) { - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7326aaed27..c87e50e804 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,7 +88,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_EPMP, }; /* Privileged specification version */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 90dc28e22e..3a2e85918a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno) static RISCVException epmp(CPURISCVState *env, int csrno) { - if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (env->priv == PRV_M && riscv_cpu_cfg(env).epmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4bc4113531..bb54899635 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked = true; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env).epmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked = false; @@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, { bool ret; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env).epmp) { if (MSECCFG_MMWP_ISSET(env)) { /* * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set -- 2.39.1