diff for duplicates of <20230217122943.24caosketyvfcc4f@orel>

diff --git a/a/1.txt b/N1/1.txt
index e675c41..9b0cff8 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -20,103 +20,103 @@ On Fri, Feb 17, 2023 at 10:50:07AM +0000, Ben Dooks wrote:
 > > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 > > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
 > > > ---
-> > > ? arch/riscv/Kconfig??????????????? | 13 ++++++
-> > > ? arch/riscv/include/asm/insn-def.h |? 4 ++
-> > > ? arch/riscv/include/asm/page.h???? |? 6 ++-
-> > > ? arch/riscv/kernel/cpufeature.c??? | 11 +++++
-> > > ? arch/riscv/lib/Makefile?????????? |? 1 +
-> > > ? arch/riscv/lib/clear_page.S?????? | 71 +++++++++++++++++++++++++++++++
-> > > ? 6 files changed, 105 insertions(+), 1 deletion(-)
-> > > ? create mode 100644 arch/riscv/lib/clear_page.S
+> > >   arch/riscv/Kconfig                | 13 ++++++
+> > >   arch/riscv/include/asm/insn-def.h |  4 ++
+> > >   arch/riscv/include/asm/page.h     |  6 ++-
+> > >   arch/riscv/kernel/cpufeature.c    | 11 +++++
+> > >   arch/riscv/lib/Makefile           |  1 +
+> > >   arch/riscv/lib/clear_page.S       | 71 +++++++++++++++++++++++++++++++
+> > >   6 files changed, 105 insertions(+), 1 deletion(-)
+> > >   create mode 100644 arch/riscv/lib/clear_page.S
 > > > 
 > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
 > > > index 029d1d3b40bd..9590a1661caf 100644
 > > > --- a/arch/riscv/Kconfig
 > > > +++ b/arch/riscv/Kconfig
 > > > @@ -456,6 +456,19 @@ config RISCV_ISA_ZICBOM
-> > > ???????? If you don't know what to do here, say Y.
+> > >          If you don't know what to do here, say Y.
 > > > +config RISCV_ISA_ZICBOZ
-> > > +??? bool "Zicboz extension support for faster zeroing of memory"
-> > > +??? depends on !XIP_KERNEL && MMU
-> > > +??? select RISCV_ALTERNATIVE
-> > > +??? default y
-> > > +??? help
-> > > +?????? Enable the use of the ZICBOZ extension (cbo.zero instruction)
-> > > +?????? when available.
+> > > +    bool "Zicboz extension support for faster zeroing of memory"
+> > > +    depends on !XIP_KERNEL && MMU
+> > > +    select RISCV_ALTERNATIVE
+> > > +    default y
+> > > +    help
+> > > +       Enable the use of the ZICBOZ extension (cbo.zero instruction)
+> > > +       when available.
 > > > +
-> > > +?????? The Zicboz extension is used for faster zeroing of memory.
+> > > +       The Zicboz extension is used for faster zeroing of memory.
 > > > +
-> > > +?????? If you don't know what to do here, say Y.
+> > > +       If you don't know what to do here, say Y.
 > > > +
-> > > ? config TOOLCHAIN_HAS_ZIHINTPAUSE
-> > > ????? bool
-> > > ????? default y
+> > >   config TOOLCHAIN_HAS_ZIHINTPAUSE
+> > >       bool
+> > >       default y
 > > > diff --git a/arch/riscv/include/asm/insn-def.h
 > > > b/arch/riscv/include/asm/insn-def.h
 > > > index e01ab51f50d2..6960beb75f32 100644
 > > > --- a/arch/riscv/include/asm/insn-def.h
 > > > +++ b/arch/riscv/include/asm/insn-def.h
 > > > @@ -192,4 +192,8 @@
-> > > ????? INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),??????? \
-> > > ???????????? RS1(base), SIMM12(2))
-> > > +#define CBO_zero(base)??????????????????????? \
-> > > +??? INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),??????? \
-> > > +?????????? RS1(base), SIMM12(4))
+> > >       INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),        \
+> > >              RS1(base), SIMM12(2))
+> > > +#define CBO_zero(base)                        \
+> > > +    INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),        \
+> > > +           RS1(base), SIMM12(4))
 > > > +
-> > > ? #endif /* __ASM_INSN_DEF_H */
+> > >   #endif /* __ASM_INSN_DEF_H */
 > > > diff --git a/arch/riscv/include/asm/page.h
 > > > b/arch/riscv/include/asm/page.h
 > > > index 9f432c1b5289..ccd168fe29d2 100644
 > > > --- a/arch/riscv/include/asm/page.h
 > > > +++ b/arch/riscv/include/asm/page.h
 > > > @@ -49,10 +49,14 @@
-> > > ? #ifndef __ASSEMBLY__
+> > >   #ifndef __ASSEMBLY__
 > > > +#ifdef CONFIG_RISCV_ISA_ZICBOZ
 > > > +void clear_page(void *page);
 > > > +#else
-> > > ? #define clear_page(pgaddr)??????????? memset((pgaddr), 0, PAGE_SIZE)
+> > >   #define clear_page(pgaddr)            memset((pgaddr), 0, PAGE_SIZE)
 > > > +#endif
-> > > ? #define copy_page(to, from)??????????? memcpy((to), (from), PAGE_SIZE)
-> > > -#define clear_user_page(pgaddr, vaddr, page)??? memset((pgaddr), 0,
+> > >   #define copy_page(to, from)            memcpy((to), (from), PAGE_SIZE)
+> > > -#define clear_user_page(pgaddr, vaddr, page)    memset((pgaddr), 0,
 > > > PAGE_SIZE)
-> > > +#define clear_user_page(pgaddr, vaddr, page)??? clear_page(pgaddr)
-> > > ? #define copy_user_page(vto, vfrom, vaddr, topg) \
-> > > ????????????? memcpy((vto), (vfrom), PAGE_SIZE)
+> > > +#define clear_user_page(pgaddr, vaddr, page)    clear_page(pgaddr)
+> > >   #define copy_user_page(vto, vfrom, vaddr, topg) \
+> > >               memcpy((vto), (vfrom), PAGE_SIZE)
 > > > diff --git a/arch/riscv/kernel/cpufeature.c
 > > > b/arch/riscv/kernel/cpufeature.c
 > > > index 74736b4f0624..42246bbfa532 100644
 > > > --- a/arch/riscv/kernel/cpufeature.c
 > > > +++ b/arch/riscv/kernel/cpufeature.c
 > > > @@ -280,6 +280,17 @@ void __init riscv_fill_hwcap(void)
-> > > ? #ifdef CONFIG_RISCV_ALTERNATIVE
-> > > ? static bool riscv_cpufeature_application_check(u32 feature, u16 data)
-> > > ? {
-> > > +??? switch (feature) {
-> > > +??? case RISCV_ISA_EXT_ZICBOZ:
-> > > +??????? /*
-> > > +???????? * Zicboz alternative applications provide the maximum
-> > > +???????? * supported block size order, or zero when it doesn't
-> > > +???????? * matter. If the current block size exceeds the maximum,
-> > > +???????? * then the alternative cannot be applied.
-> > > +???????? */
-> > > +??????? return data == 0 || riscv_cboz_block_size <= (1U << data);
-> > > +??? }
+> > >   #ifdef CONFIG_RISCV_ALTERNATIVE
+> > >   static bool riscv_cpufeature_application_check(u32 feature, u16 data)
+> > >   {
+> > > +    switch (feature) {
+> > > +    case RISCV_ISA_EXT_ZICBOZ:
+> > > +        /*
+> > > +         * Zicboz alternative applications provide the maximum
+> > > +         * supported block size order, or zero when it doesn't
+> > > +         * matter. If the current block size exceeds the maximum,
+> > > +         * then the alternative cannot be applied.
+> > > +         */
+> > > +        return data == 0 || riscv_cboz_block_size <= (1U << data);
+> > > +    }
 > 
 > 
 > 
 > > > +
-> > > ????? return data == 0;
-> > > ? }
+> > >       return data == 0;
+> > >   }
 > > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
 > > > index 6c74b0bedd60..26cb2502ecf8 100644
 > > > --- a/arch/riscv/lib/Makefile
 > > > +++ b/arch/riscv/lib/Makefile
-> > > @@ -8,5 +8,6 @@ lib-y??????????? += strlen.o
-> > > ? lib-y??????????? += strncmp.o
-> > > ? lib-$(CONFIG_MMU)??? += uaccess.o
-> > > ? lib-$(CONFIG_64BIT)??? += tishift.o
-> > > +lib-$(CONFIG_RISCV_ISA_ZICBOZ)??? += clear_page.o
-> > > ? obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
+> > > @@ -8,5 +8,6 @@ lib-y            += strlen.o
+> > >   lib-y            += strncmp.o
+> > >   lib-$(CONFIG_MMU)    += uaccess.o
+> > >   lib-$(CONFIG_64BIT)    += tishift.o
+> > > +lib-$(CONFIG_RISCV_ISA_ZICBOZ)    += clear_page.o
+> > >   obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
 > > > diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S
 > > > new file mode 100644
 > > > index 000000000000..5b851e727f7c
@@ -135,8 +135,8 @@ On Fri, Feb 17, 2023 at 10:50:07AM +0000, Ben Dooks wrote:
 > > > +#include <asm/insn-def.h>
 > > > +#include <asm/page.h>
 > > > +
-> > > +#define CBOZ_ALT(order, old, new)??? \
-> > > +??? ALTERNATIVE(old, new, order, RISCV_ISA_EXT_ZICBOZ,
+> > > +#define CBOZ_ALT(order, old, new)    \
+> > > +    ALTERNATIVE(old, new, order, RISCV_ISA_EXT_ZICBOZ,
 > > > CONFIG_RISCV_ISA_ZICBOZ)
 > > 
 > > I thought this was meant to be a CPUFEATURE_ZICBOZ thing for the
@@ -165,3 +165,8 @@ rather break errata_id into two parts: id and application-data.
 
 Thanks,
 drew
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index 7bdf827..3bba9de 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,9 +3,22 @@
  "ref\04a25cf89-bcf0-e78c-a8ab-7ba0c4f8e2bf@codethink.co.uk\0"
  "ref\0b348f0cc-4868-2924-9935-00ec18b36da9@codethink.co.uk\0"
  "From\0Andrew Jones <ajones@ventanamicro.com>\0"
- "Subject\0[PATCH v4 6/8] RISC-V: Use Zicboz in clear_page when available\0"
+ "Subject\0Re: [PATCH v4 6/8] RISC-V: Use Zicboz in clear_page when available\0"
  "Date\0Fri, 17 Feb 2023 13:29:43 +0100\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0Ben Dooks <ben.dooks@codethink.co.uk>\0"
+ "Cc\0linux-riscv@lists.infradead.org"
+  kvm-riscv@lists.infradead.org
+  devicetree@vger.kernel.org
+  'Anup Patel ' <apatel@ventanamicro.com>
+  'Palmer Dabbelt ' <palmer@dabbelt.com>
+  'Paul Walmsley ' <paul.walmsley@sifive.com>
+  'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>
+  'Atish Patra ' <atishp@rivosinc.com>
+  'Heiko Stuebner ' <heiko@sntech.de>
+  'Jisheng Zhang ' <jszhang@kernel.org>
+  'Rob Herring ' <robh@kernel.org>
+  'Albert Ou ' <aou@eecs.berkeley.edu>
+ " 'Conor Dooley ' <conor.dooley@microchip.com>\0"
  "\00:1\0"
  "b\0"
  "On Fri, Feb 17, 2023 at 10:50:07AM +0000, Ben Dooks wrote:\n"
@@ -30,103 +43,103 @@
  "> > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>\n"
  "> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>\n"
  "> > > ---\n"
- "> > > ? arch/riscv/Kconfig??????????????? | 13 ++++++\n"
- "> > > ? arch/riscv/include/asm/insn-def.h |? 4 ++\n"
- "> > > ? arch/riscv/include/asm/page.h???? |? 6 ++-\n"
- "> > > ? arch/riscv/kernel/cpufeature.c??? | 11 +++++\n"
- "> > > ? arch/riscv/lib/Makefile?????????? |? 1 +\n"
- "> > > ? arch/riscv/lib/clear_page.S?????? | 71 +++++++++++++++++++++++++++++++\n"
- "> > > ? 6 files changed, 105 insertions(+), 1 deletion(-)\n"
- "> > > ? create mode 100644 arch/riscv/lib/clear_page.S\n"
+ "> > > \302\240 arch/riscv/Kconfig\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 | 13 ++++++\n"
+ "> > > \302\240 arch/riscv/include/asm/insn-def.h |\302\240 4 ++\n"
+ "> > > \302\240 arch/riscv/include/asm/page.h\302\240\302\240\302\240\302\240 |\302\240 6 ++-\n"
+ "> > > \302\240 arch/riscv/kernel/cpufeature.c\302\240\302\240\302\240 | 11 +++++\n"
+ "> > > \302\240 arch/riscv/lib/Makefile\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 |\302\240 1 +\n"
+ "> > > \302\240 arch/riscv/lib/clear_page.S\302\240\302\240\302\240\302\240\302\240\302\240 | 71 +++++++++++++++++++++++++++++++\n"
+ "> > > \302\240 6 files changed, 105 insertions(+), 1 deletion(-)\n"
+ "> > > \302\240 create mode 100644 arch/riscv/lib/clear_page.S\n"
  "> > > \n"
  "> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\n"
  "> > > index 029d1d3b40bd..9590a1661caf 100644\n"
  "> > > --- a/arch/riscv/Kconfig\n"
  "> > > +++ b/arch/riscv/Kconfig\n"
  "> > > @@ -456,6 +456,19 @@ config RISCV_ISA_ZICBOM\n"
- "> > > ???????? If you don't know what to do here, say Y.\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 If you don't know what to do here, say Y.\n"
  "> > > +config RISCV_ISA_ZICBOZ\n"
- "> > > +??? bool \"Zicboz extension support for faster zeroing of memory\"\n"
- "> > > +??? depends on !XIP_KERNEL && MMU\n"
- "> > > +??? select RISCV_ALTERNATIVE\n"
- "> > > +??? default y\n"
- "> > > +??? help\n"
- "> > > +?????? Enable the use of the ZICBOZ extension (cbo.zero instruction)\n"
- "> > > +?????? when available.\n"
+ "> > > +\302\240\302\240\302\240 bool \"Zicboz extension support for faster zeroing of memory\"\n"
+ "> > > +\302\240\302\240\302\240 depends on !XIP_KERNEL && MMU\n"
+ "> > > +\302\240\302\240\302\240 select RISCV_ALTERNATIVE\n"
+ "> > > +\302\240\302\240\302\240 default y\n"
+ "> > > +\302\240\302\240\302\240 help\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240 Enable the use of the ZICBOZ extension (cbo.zero instruction)\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240 when available.\n"
  "> > > +\n"
- "> > > +?????? The Zicboz extension is used for faster zeroing of memory.\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240 The Zicboz extension is used for faster zeroing of memory.\n"
  "> > > +\n"
- "> > > +?????? If you don't know what to do here, say Y.\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240 If you don't know what to do here, say Y.\n"
  "> > > +\n"
- "> > > ? config TOOLCHAIN_HAS_ZIHINTPAUSE\n"
- "> > > ????? bool\n"
- "> > > ????? default y\n"
+ "> > > \302\240 config TOOLCHAIN_HAS_ZIHINTPAUSE\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240 bool\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240 default y\n"
  "> > > diff --git a/arch/riscv/include/asm/insn-def.h\n"
  "> > > b/arch/riscv/include/asm/insn-def.h\n"
  "> > > index e01ab51f50d2..6960beb75f32 100644\n"
  "> > > --- a/arch/riscv/include/asm/insn-def.h\n"
  "> > > +++ b/arch/riscv/include/asm/insn-def.h\n"
  "> > > @@ -192,4 +192,8 @@\n"
- "> > > ????? INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),??????? \\\n"
- "> > > ???????????? RS1(base), SIMM12(2))\n"
- "> > > +#define CBO_zero(base)??????????????????????? \\\n"
- "> > > +??? INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),??????? \\\n"
- "> > > +?????????? RS1(base), SIMM12(4))\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240 INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),\302\240\302\240\302\240\302\240\302\240\302\240\302\240 \\\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 RS1(base), SIMM12(2))\n"
+ "> > > +#define CBO_zero(base)\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 \\\n"
+ "> > > +\302\240\302\240\302\240 INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),\302\240\302\240\302\240\302\240\302\240\302\240\302\240 \\\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 RS1(base), SIMM12(4))\n"
  "> > > +\n"
- "> > > ? #endif /* __ASM_INSN_DEF_H */\n"
+ "> > > \302\240 #endif /* __ASM_INSN_DEF_H */\n"
  "> > > diff --git a/arch/riscv/include/asm/page.h\n"
  "> > > b/arch/riscv/include/asm/page.h\n"
  "> > > index 9f432c1b5289..ccd168fe29d2 100644\n"
  "> > > --- a/arch/riscv/include/asm/page.h\n"
  "> > > +++ b/arch/riscv/include/asm/page.h\n"
  "> > > @@ -49,10 +49,14 @@\n"
- "> > > ? #ifndef __ASSEMBLY__\n"
+ "> > > \302\240 #ifndef __ASSEMBLY__\n"
  "> > > +#ifdef CONFIG_RISCV_ISA_ZICBOZ\n"
  "> > > +void clear_page(void *page);\n"
  "> > > +#else\n"
- "> > > ? #define clear_page(pgaddr)??????????? memset((pgaddr), 0, PAGE_SIZE)\n"
+ "> > > \302\240 #define clear_page(pgaddr)\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 memset((pgaddr), 0, PAGE_SIZE)\n"
  "> > > +#endif\n"
- "> > > ? #define copy_page(to, from)??????????? memcpy((to), (from), PAGE_SIZE)\n"
- "> > > -#define clear_user_page(pgaddr, vaddr, page)??? memset((pgaddr), 0,\n"
+ "> > > \302\240 #define copy_page(to, from)\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 memcpy((to), (from), PAGE_SIZE)\n"
+ "> > > -#define clear_user_page(pgaddr, vaddr, page)\302\240\302\240\302\240 memset((pgaddr), 0,\n"
  "> > > PAGE_SIZE)\n"
- "> > > +#define clear_user_page(pgaddr, vaddr, page)??? clear_page(pgaddr)\n"
- "> > > ? #define copy_user_page(vto, vfrom, vaddr, topg) \\\n"
- "> > > ????????????? memcpy((vto), (vfrom), PAGE_SIZE)\n"
+ "> > > +#define clear_user_page(pgaddr, vaddr, page)\302\240\302\240\302\240 clear_page(pgaddr)\n"
+ "> > > \302\240 #define copy_user_page(vto, vfrom, vaddr, topg) \\\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 memcpy((vto), (vfrom), PAGE_SIZE)\n"
  "> > > diff --git a/arch/riscv/kernel/cpufeature.c\n"
  "> > > b/arch/riscv/kernel/cpufeature.c\n"
  "> > > index 74736b4f0624..42246bbfa532 100644\n"
  "> > > --- a/arch/riscv/kernel/cpufeature.c\n"
  "> > > +++ b/arch/riscv/kernel/cpufeature.c\n"
  "> > > @@ -280,6 +280,17 @@ void __init riscv_fill_hwcap(void)\n"
- "> > > ? #ifdef CONFIG_RISCV_ALTERNATIVE\n"
- "> > > ? static bool riscv_cpufeature_application_check(u32 feature, u16 data)\n"
- "> > > ? {\n"
- "> > > +??? switch (feature) {\n"
- "> > > +??? case RISCV_ISA_EXT_ZICBOZ:\n"
- "> > > +??????? /*\n"
- "> > > +???????? * Zicboz alternative applications provide the maximum\n"
- "> > > +???????? * supported block size order, or zero when it doesn't\n"
- "> > > +???????? * matter. If the current block size exceeds the maximum,\n"
- "> > > +???????? * then the alternative cannot be applied.\n"
- "> > > +???????? */\n"
- "> > > +??????? return data == 0 || riscv_cboz_block_size <= (1U << data);\n"
- "> > > +??? }\n"
+ "> > > \302\240 #ifdef CONFIG_RISCV_ALTERNATIVE\n"
+ "> > > \302\240 static bool riscv_cpufeature_application_check(u32 feature, u16 data)\n"
+ "> > > \302\240 {\n"
+ "> > > +\302\240\302\240\302\240 switch (feature) {\n"
+ "> > > +\302\240\302\240\302\240 case RISCV_ISA_EXT_ZICBOZ:\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 /*\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * Zicboz alternative applications provide the maximum\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * supported block size order, or zero when it doesn't\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * matter. If the current block size exceeds the maximum,\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 * then the alternative cannot be applied.\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 */\n"
+ "> > > +\302\240\302\240\302\240\302\240\302\240\302\240\302\240 return data == 0 || riscv_cboz_block_size <= (1U << data);\n"
+ "> > > +\302\240\302\240\302\240 }\n"
  "> \n"
  "> \n"
  "> \n"
  "> > > +\n"
- "> > > ????? return data == 0;\n"
- "> > > ? }\n"
+ "> > > \302\240\302\240\302\240\302\240\302\240 return data == 0;\n"
+ "> > > \302\240 }\n"
  "> > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile\n"
  "> > > index 6c74b0bedd60..26cb2502ecf8 100644\n"
  "> > > --- a/arch/riscv/lib/Makefile\n"
  "> > > +++ b/arch/riscv/lib/Makefile\n"
- "> > > @@ -8,5 +8,6 @@ lib-y??????????? += strlen.o\n"
- "> > > ? lib-y??????????? += strncmp.o\n"
- "> > > ? lib-$(CONFIG_MMU)??? += uaccess.o\n"
- "> > > ? lib-$(CONFIG_64BIT)??? += tishift.o\n"
- "> > > +lib-$(CONFIG_RISCV_ISA_ZICBOZ)??? += clear_page.o\n"
- "> > > ? obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o\n"
+ "> > > @@ -8,5 +8,6 @@ lib-y\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 += strlen.o\n"
+ "> > > \302\240 lib-y\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240\302\240 += strncmp.o\n"
+ "> > > \302\240 lib-$(CONFIG_MMU)\302\240\302\240\302\240 += uaccess.o\n"
+ "> > > \302\240 lib-$(CONFIG_64BIT)\302\240\302\240\302\240 += tishift.o\n"
+ "> > > +lib-$(CONFIG_RISCV_ISA_ZICBOZ)\302\240\302\240\302\240 += clear_page.o\n"
+ "> > > \302\240 obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o\n"
  "> > > diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S\n"
  "> > > new file mode 100644\n"
  "> > > index 000000000000..5b851e727f7c\n"
@@ -145,8 +158,8 @@
  "> > > +#include <asm/insn-def.h>\n"
  "> > > +#include <asm/page.h>\n"
  "> > > +\n"
- "> > > +#define CBOZ_ALT(order, old, new)??? \\\n"
- "> > > +??? ALTERNATIVE(old, new, order, RISCV_ISA_EXT_ZICBOZ,\n"
+ "> > > +#define CBOZ_ALT(order, old, new)\302\240\302\240\302\240 \\\n"
+ "> > > +\302\240\302\240\302\240 ALTERNATIVE(old, new, order, RISCV_ISA_EXT_ZICBOZ,\n"
  "> > > CONFIG_RISCV_ISA_ZICBOZ)\n"
  "> > \n"
  "> > I thought this was meant to be a CPUFEATURE_ZICBOZ thing for the\n"
@@ -174,6 +187,11 @@
  "rather break errata_id into two parts: id and application-data.\n"
  "\n"
  "Thanks,\n"
- drew
+ "drew\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
-c128b660468b451edf7f55d0c9f1b268e1819e4c79e667748fb9a18f6a6d0f22
+6f8fa50f641b7bad17e994ae4c15d3d278bac65afb884ee69f1d606fb57b3ecd
