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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id z12-20020a1709064e0c00b008c405ebc32esm3249911eju.28.2023.02.20.11.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 11:47:27 -0800 (PST) Date: Mon, 20 Feb 2023 20:47:26 +0100 From: Andrew Jones To: Sunil V L Cc: Palmer Dabbelt , Albert Ou , Paul Walmsley , "Rafael J . Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley , Anup Patel , Atish Patra , "Rafael J . Wysocki" Subject: Re: [PATCH V2 15/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Message-ID: <20230220194726.meppdac4y7qdjsoj@orel> References: <20230216182043.1946553-1-sunilvl@ventanamicro.com> <20230216182043.1946553-16-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230216182043.1946553-16-sunilvl@ventanamicro.com> Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Thu, Feb 16, 2023 at 11:50:37PM +0530, Sunil V L wrote: > Refactor the timer init function such that few things can be > shared by both DT and ACPI based platforms. > > Co-developed-by: Anup Patel > Signed-off-by: Anup Patel > Signed-off-by: Sunil V L > Acked-by: Rafael J. Wysocki > --- > drivers/clocksource/timer-riscv.c | 82 +++++++++++++++---------------- > 1 file changed, 40 insertions(+), 42 deletions(-) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 1b4b36df5484..2ae8e300d303 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -119,61 +119,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) > return IRQ_HANDLED; > } > > -static int __init riscv_timer_init_dt(struct device_node *n) > +static int __init riscv_timer_init_common(void) > { > - int cpuid, error; > - unsigned long hartid; > - struct device_node *child; > - struct irq_domain *domain; > + int error; > + struct irq_domain *domain = NULL; domain is always assigned below, so we don't need to set it NULL here. > + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); > > - error = riscv_of_processor_hartid(n, &hartid); > - if (error < 0) { > - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", > - n, hartid); > - return error; > - } > - > - cpuid = riscv_hartid_to_cpuid(hartid); > - if (cpuid < 0) { > - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); > - return cpuid; > - } > - > - if (cpuid != smp_processor_id()) > - return 0; > - > - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > - if (child) { > - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, > - "riscv,timer-cannot-wake-cpu"); > - of_node_put(child); > - } > - > - domain = NULL; > - child = of_get_compatible_child(n, "riscv,cpu-intc"); > - if (!child) { > - pr_err("Failed to find INTC node [%pOF]\n", n); > - return -ENODEV; > - } > - domain = irq_find_host(child); > - of_node_put(child); > + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); > if (!domain) { > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); > + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", > + intc_fwnode); > return -ENODEV; > } > > riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); > if (!riscv_clock_event_irq) { > - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); > + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); > return -ENODEV; > } > > - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", > - __func__, cpuid, hartid); > error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); > if (error) { > - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("RISCV timer registration failed [%d]\n", error); > return error; > } > > @@ -202,4 +169,35 @@ static int __init riscv_timer_init_dt(struct device_node *n) > return error; > } > > +static int __init riscv_timer_init_dt(struct device_node *n) > +{ > + int cpuid, error; > + unsigned long hartid; > + struct device_node *child; > + > + error = riscv_of_processor_hartid(n, &hartid); > + if (error < 0) { > + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", > + n, hartid); > + return error; > + } > + > + cpuid = riscv_hartid_to_cpuid(hartid); > + if (cpuid < 0) { > + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); > + return cpuid; > + } > + > + if (cpuid != smp_processor_id()) > + return 0; > + > + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > + if (child) { > + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, > + "riscv,timer-cannot-wake-cpu"); > + of_node_put(child); > + } need blank line here > + return riscv_timer_init_common(); > +} > + > TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); > -- > 2.34.1 > Otherwise, Reviewed-by: Andrew Jones From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9860C636D6 for ; Mon, 20 Feb 2023 19:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id z12-20020a1709064e0c00b008c405ebc32esm3249911eju.28.2023.02.20.11.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 11:47:27 -0800 (PST) Date: Mon, 20 Feb 2023 20:47:26 +0100 From: Andrew Jones To: Sunil V L Cc: Palmer Dabbelt , Albert Ou , Paul Walmsley , "Rafael J . Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley , Anup Patel , Atish Patra , "Rafael J . Wysocki" Subject: Re: [PATCH V2 15/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Message-ID: <20230220194726.meppdac4y7qdjsoj@orel> References: <20230216182043.1946553-1-sunilvl@ventanamicro.com> <20230216182043.1946553-16-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230216182043.1946553-16-sunilvl@ventanamicro.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230220_114733_263693_E259D829 X-CRM114-Status: GOOD ( 22.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Feb 16, 2023 at 11:50:37PM +0530, Sunil V L wrote: > Refactor the timer init function such that few things can be > shared by both DT and ACPI based platforms. > > Co-developed-by: Anup Patel > Signed-off-by: Anup Patel > Signed-off-by: Sunil V L > Acked-by: Rafael J. Wysocki > --- > drivers/clocksource/timer-riscv.c | 82 +++++++++++++++---------------- > 1 file changed, 40 insertions(+), 42 deletions(-) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 1b4b36df5484..2ae8e300d303 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -119,61 +119,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) > return IRQ_HANDLED; > } > > -static int __init riscv_timer_init_dt(struct device_node *n) > +static int __init riscv_timer_init_common(void) > { > - int cpuid, error; > - unsigned long hartid; > - struct device_node *child; > - struct irq_domain *domain; > + int error; > + struct irq_domain *domain = NULL; domain is always assigned below, so we don't need to set it NULL here. > + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); > > - error = riscv_of_processor_hartid(n, &hartid); > - if (error < 0) { > - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", > - n, hartid); > - return error; > - } > - > - cpuid = riscv_hartid_to_cpuid(hartid); > - if (cpuid < 0) { > - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); > - return cpuid; > - } > - > - if (cpuid != smp_processor_id()) > - return 0; > - > - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > - if (child) { > - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, > - "riscv,timer-cannot-wake-cpu"); > - of_node_put(child); > - } > - > - domain = NULL; > - child = of_get_compatible_child(n, "riscv,cpu-intc"); > - if (!child) { > - pr_err("Failed to find INTC node [%pOF]\n", n); > - return -ENODEV; > - } > - domain = irq_find_host(child); > - of_node_put(child); > + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); > if (!domain) { > - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); > + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", > + intc_fwnode); > return -ENODEV; > } > > riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); > if (!riscv_clock_event_irq) { > - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); > + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); > return -ENODEV; > } > > - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", > - __func__, cpuid, hartid); > error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); > if (error) { > - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("RISCV timer registration failed [%d]\n", error); > return error; > } > > @@ -202,4 +169,35 @@ static int __init riscv_timer_init_dt(struct device_node *n) > return error; > } > > +static int __init riscv_timer_init_dt(struct device_node *n) > +{ > + int cpuid, error; > + unsigned long hartid; > + struct device_node *child; > + > + error = riscv_of_processor_hartid(n, &hartid); > + if (error < 0) { > + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", > + n, hartid); > + return error; > + } > + > + cpuid = riscv_hartid_to_cpuid(hartid); > + if (cpuid < 0) { > + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); > + return cpuid; > + } > + > + if (cpuid != smp_processor_id()) > + return 0; > + > + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); > + if (child) { > + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, > + "riscv,timer-cannot-wake-cpu"); > + of_node_put(child); > + } need blank line here > + return riscv_timer_init_common(); > +} > + > TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); > -- > 2.34.1 > Otherwise, Reviewed-by: Andrew Jones _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv