diff for duplicates of <20230221190916.572454-6-ajones@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index 2074bde..5fa737c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -98,3 +98,9 @@ index 6102b6bb5db3..0594989ead63 100644 oldptr = ALT_OLD_PTR(alt); -- 2.39.1 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index d75b128..38dcf9c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,20 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v5 5/8] riscv: cpufeatures: Put the upper 16 bits of patch ID to work\0" "Date\0Tue, 21 Feb 2023 20:09:13 +0100\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + devicetree@vger.kernel.org + " kvm-riscv@lists.infradead.org\0" + "Cc\0'Rob Herring ' <robh@kernel.org>" + 'Jisheng Zhang ' <jszhang@kernel.org> + 'Anup Patel ' <apatel@ventanamicro.com> + 'Conor Dooley ' <conor.dooley@microchip.com> + 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org> + 'Heiko Stuebner ' <heiko@sntech.de> + 'Paul Walmsley ' <paul.walmsley@sifive.com> + 'Palmer Dabbelt ' <palmer@dabbelt.com> + 'Albert Ou ' <aou@eecs.berkeley.edu> + 'Ben Dooks ' <ben.dooks@codethink.co.uk> + " 'Atish Patra ' <atishp@rivosinc.com>\0" "\00:1\0" "b\0" "cpufeature IDs are consecutive integers starting at 26, so a 32-bit\n" @@ -104,6 +117,12 @@ " \n" " \t\toldptr = ALT_OLD_PTR(alt);\n" "-- \n" - 2.39.1 + "2.39.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -e76ef9fdb9425a74a7fa2ac1e10c2c0a4b168be1be6beb172785e19f0830408e +6f2e3e1c872885b60f6972cb46bd197f6a70157cdc69fad3bae9426f7277bf39
diff --git a/a/content_digest b/N2/content_digest index d75b128..dda0b44 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,7 +2,20 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v5 5/8] riscv: cpufeatures: Put the upper 16 bits of patch ID to work\0" "Date\0Tue, 21 Feb 2023 20:09:13 +0100\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + devicetree@vger.kernel.org + " kvm-riscv@lists.infradead.org\0" + "Cc\0'Rob Herring ' <robh@kernel.org>" + 'Jisheng Zhang ' <jszhang@kernel.org> + 'Anup Patel ' <apatel@ventanamicro.com> + 'Conor Dooley ' <conor.dooley@microchip.com> + 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org> + 'Heiko Stuebner ' <heiko@sntech.de> + 'Paul Walmsley ' <paul.walmsley@sifive.com> + 'Palmer Dabbelt ' <palmer@dabbelt.com> + 'Albert Ou ' <aou@eecs.berkeley.edu> + 'Ben Dooks ' <ben.dooks@codethink.co.uk> + " 'Atish Patra ' <atishp@rivosinc.com>\0" "\00:1\0" "b\0" "cpufeature IDs are consecutive integers starting at 26, so a 32-bit\n" @@ -106,4 +119,4 @@ "-- \n" 2.39.1 -e76ef9fdb9425a74a7fa2ac1e10c2c0a4b168be1be6beb172785e19f0830408e +251e15bcddd2a3e379208c1b1598f4e81c8bcdd9cf2c493cf674c12a8c65870f
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