diff for duplicates of <20230224162631.405473-6-ajones@ventanamicro.com> diff --git a/a/1.txt b/N1/1.txt index a6d70e5..0232b6c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -104,3 +104,9 @@ index 538779d03311..d424cd76beb1 100644 oldptr = ALT_OLD_PTR(alt); -- 2.39.1 + + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index 278de49..d3b874d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,21 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v6 5/8] RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work\0" "Date\0Fri, 24 Feb 2023 17:26:28 +0100\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + kvm-riscv@lists.infradead.org + " devicetree@vger.kernel.org\0" + "Cc\0'Conor Dooley ' <conor.dooley@microchip.com>" + 'Paul Walmsley ' <paul.walmsley@sifive.com> + 'Palmer Dabbelt ' <palmer@dabbelt.com> + 'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk> + 'Ben Dooks ' <ben.dooks@codethink.co.uk> + 'Atish Patra ' <atishp@rivosinc.com> + 'Albert Ou ' <aou@eecs.berkeley.edu> + 'Anup Patel ' <apatel@ventanamicro.com> + 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org> + 'Rob Herring ' <robh@kernel.org> + 'Jisheng Zhang ' <jszhang@kernel.org> + " 'Heiko Stuebner ' <heiko@sntech.de>\0" "\00:1\0" "b\0" "cpufeature IDs are consecutive integers starting at 26, so a 32-bit\n" @@ -110,6 +124,12 @@ " \n" " \t\toldptr = ALT_OLD_PTR(alt);\n" "-- \n" - 2.39.1 + "2.39.1\n" + "\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -697b922b818c36902e70c6a50358cea1479905207b930485e3126a1e2da400a4 +d21541b9040d9114839b75f760ff726942bde6d2845899f5db0525ce57991333
diff --git a/a/content_digest b/N2/content_digest index 278de49..4741518 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,7 +2,21 @@ "From\0Andrew Jones <ajones@ventanamicro.com>\0" "Subject\0[PATCH v6 5/8] RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work\0" "Date\0Fri, 24 Feb 2023 17:26:28 +0100\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0linux-riscv@lists.infradead.org" + kvm-riscv@lists.infradead.org + " devicetree@vger.kernel.org\0" + "Cc\0'Conor Dooley ' <conor.dooley@microchip.com>" + 'Paul Walmsley ' <paul.walmsley@sifive.com> + 'Palmer Dabbelt ' <palmer@dabbelt.com> + 'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk> + 'Ben Dooks ' <ben.dooks@codethink.co.uk> + 'Atish Patra ' <atishp@rivosinc.com> + 'Albert Ou ' <aou@eecs.berkeley.edu> + 'Anup Patel ' <apatel@ventanamicro.com> + 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org> + 'Rob Herring ' <robh@kernel.org> + 'Jisheng Zhang ' <jszhang@kernel.org> + " 'Heiko Stuebner ' <heiko@sntech.de>\0" "\00:1\0" "b\0" "cpufeature IDs are consecutive integers starting at 26, so a 32-bit\n" @@ -112,4 +126,4 @@ "-- \n" 2.39.1 -697b922b818c36902e70c6a50358cea1479905207b930485e3126a1e2da400a4 +7dc3880d0a6212072268faaa6d1f891a535d48af147c4929a973013af5c13845
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