diff for duplicates of <202302251633.Tsr3ebfs-lkp@intel.com> diff --git a/a/1.txt b/N1/1.txt index 11021f9..820d1cf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -7,7 +7,7 @@ I love your patch! Perhaps something to improve: url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-Rename-__switch_to_aux-fpu/20230225-011059 patch link: https://lore.kernel.org/r/20230224170118.16766-20-andy.chiu%40sifive.com patch subject: [PATCH -next v14 19/19] riscv: Enable Vector code to be built -config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp at intel.com/config) +config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross @@ -23,7 +23,7 @@ reproduce (this is a W=1 build): If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> -| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp at intel.com/ +| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp@intel.com/ All warnings (new ones prefixed by >>): @@ -52,3 +52,8 @@ b57b7b7279ef75 Andy Chiu 2023-02-24 79 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests + +_______________________________________________ +linux-riscv mailing list +linux-riscv@lists.infradead.org +http://lists.infradead.org/mailman/listinfo/linux-riscv diff --git a/a/content_digest b/N1/content_digest index 5acb565..751bf92 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,21 @@ "ref\020230224170118.16766-20-andy.chiu@sifive.com\0" "From\0kernel test robot <lkp@intel.com>\0" - "Subject\0[PATCH -next v14 19/19] riscv: Enable Vector code to be built\0" + "Subject\0Re: [PATCH -next v14 19/19] riscv: Enable Vector code to be built\0" "Date\0Sat, 25 Feb 2023 16:28:02 +0800\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Andy Chiu <andy.chiu@sifive.com>" + linux-riscv@lists.infradead.org + palmer@dabbelt.com + anup@brainfault.org + atishp@atishpatra.org + kvm-riscv@lists.infradead.org + " kvm@vger.kernel.org\0" + "Cc\0oe-kbuild-all@lists.linux.dev" + vineetg@rivosinc.com + greentime.hu@sifive.com + guoren@linux.alibaba.com + Andy Chiu <andy.chiu@sifive.com> + Paul Walmsley <paul.walmsley@sifive.com> + " Albert Ou <aou@eecs.berkeley.edu>\0" "\00:1\0" "b\0" "Hi Andy,\n" @@ -14,7 +27,7 @@ "url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-Rename-__switch_to_aux-fpu/20230225-011059\n" "patch link: https://lore.kernel.org/r/20230224170118.16766-20-andy.chiu%40sifive.com\n" "patch subject: [PATCH -next v14 19/19] riscv: Enable Vector code to be built\n" - "config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp at intel.com/config)\n" + "config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp@intel.com/config)\n" "compiler: riscv32-linux-gcc (GCC) 12.1.0\n" "reproduce (this is a W=1 build):\n" " wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n" @@ -30,7 +43,7 @@ "\n" "If you fix the issue, kindly add following tag where applicable\n" "| Reported-by: kernel test robot <lkp@intel.com>\n" - "| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp at intel.com/\n" + "| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp@intel.com/\n" "\n" "All warnings (new ones prefixed by >>):\n" "\n" @@ -58,6 +71,11 @@ "\n" "-- \n" "0-DAY CI Kernel Test Service\n" - https://github.com/intel/lkp-tests + "https://github.com/intel/lkp-tests\n" + "\n" + "_______________________________________________\n" + "linux-riscv mailing list\n" + "linux-riscv@lists.infradead.org\n" + http://lists.infradead.org/mailman/listinfo/linux-riscv -faeb20a33078c3d190b1aeb785bc0fc7e6c0c2c2227cdaec4a758f51c2aa5f0c +9223228686b3000117db1266706a54042f0927103f3eb436a43a5208ef4175de
diff --git a/a/1.txt b/N2/1.txt index 11021f9..82bdff4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -7,7 +7,7 @@ I love your patch! Perhaps something to improve: url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-Rename-__switch_to_aux-fpu/20230225-011059 patch link: https://lore.kernel.org/r/20230224170118.16766-20-andy.chiu%40sifive.com patch subject: [PATCH -next v14 19/19] riscv: Enable Vector code to be built -config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp at intel.com/config) +config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp@intel.com/config) compiler: riscv32-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross @@ -23,7 +23,7 @@ reproduce (this is a W=1 build): If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> -| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp at intel.com/ +| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp@intel.com/ All warnings (new ones prefixed by >>): diff --git a/a/content_digest b/N2/content_digest index 5acb565..69f6df2 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,8 +1,21 @@ "ref\020230224170118.16766-20-andy.chiu@sifive.com\0" "From\0kernel test robot <lkp@intel.com>\0" - "Subject\0[PATCH -next v14 19/19] riscv: Enable Vector code to be built\0" + "Subject\0Re: [PATCH -next v14 19/19] riscv: Enable Vector code to be built\0" "Date\0Sat, 25 Feb 2023 16:28:02 +0800\0" - "To\0kvm-riscv@lists.infradead.org\0" + "To\0Andy Chiu <andy.chiu@sifive.com>" + linux-riscv@lists.infradead.org + palmer@dabbelt.com + anup@brainfault.org + atishp@atishpatra.org + kvm-riscv@lists.infradead.org + " kvm@vger.kernel.org\0" + "Cc\0oe-kbuild-all@lists.linux.dev" + vineetg@rivosinc.com + greentime.hu@sifive.com + guoren@linux.alibaba.com + Andy Chiu <andy.chiu@sifive.com> + Paul Walmsley <paul.walmsley@sifive.com> + " Albert Ou <aou@eecs.berkeley.edu>\0" "\00:1\0" "b\0" "Hi Andy,\n" @@ -14,7 +27,7 @@ "url: https://github.com/intel-lab-lkp/linux/commits/Andy-Chiu/riscv-Rename-__switch_to_aux-fpu/20230225-011059\n" "patch link: https://lore.kernel.org/r/20230224170118.16766-20-andy.chiu%40sifive.com\n" "patch subject: [PATCH -next v14 19/19] riscv: Enable Vector code to be built\n" - "config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp at intel.com/config)\n" + "config: riscv-randconfig-r042-20230223 (https://download.01.org/0day-ci/archive/20230225/202302251633.Tsr3ebfs-lkp@intel.com/config)\n" "compiler: riscv32-linux-gcc (GCC) 12.1.0\n" "reproduce (this is a W=1 build):\n" " wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n" @@ -30,7 +43,7 @@ "\n" "If you fix the issue, kindly add following tag where applicable\n" "| Reported-by: kernel test robot <lkp@intel.com>\n" - "| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp at intel.com/\n" + "| Link: https://lore.kernel.org/oe-kbuild-all/202302251633.Tsr3ebfs-lkp@intel.com/\n" "\n" "All warnings (new ones prefixed by >>):\n" "\n" @@ -60,4 +73,4 @@ "0-DAY CI Kernel Test Service\n" https://github.com/intel/lkp-tests -faeb20a33078c3d190b1aeb785bc0fc7e6c0c2c2227cdaec4a758f51c2aa5f0c +225a092fa46a8ea1b92f4db2220704dd9c96c983bd3c3b01833bc1f2fc7706e0
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